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LTM4673 Datasheet(PDF) 85 Page - Analog Devices

Part # LTM4673
Description  Low VOUT Quad 31.25A or Single 125A μModule Regulator with Digital Power System Management
PDF  132 Pages
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

LTM4673 Datasheet(HTML) 85 Page - Analog Devices

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LTM4683
85
Rev. 0
For more information www.analog.com
PMBus COMMAND DETAILS
MFR_ADDRESS
The MFR_ADDRESS command byte sets the 7 bits of the PMBus subordinate address for this device.
Setting this command to a value of 0x80 disables device addressing. The GLOBAL device address, 0x5A and 0x5B,
cannot be deactivated. If RCONFIG is set to ignore, the ASEL_nn pins are still used to determine the LSB of the channel
address. If the ASEL_01 and ASEL_23 pins are both open, the LTM4683 will use the address value stored in NVM.
If the ASEL_nn pins are open, the LTM4683 will use the lower 4 bits of the MFR_ADDRESS value stored in NVM to
construct the effective address of the part.
This command has one data byte.
MFR_RAIL_ADDRESS
The MFR_RAIL_ADDRESS command enables direct device address access to the PAGE-activated channel. The value
of this command should be common to all devices attached to a single power supply rail.
The user should only perform command writes to this address. If a read is performed from this address and the rail
devices do not respond with EXACTLY the same value, the LTM4683 will detect bus contention and may set a CML
communications fault.
Setting this command to a value of 0x80 disables rail device addressing for the channel.
This command has one data byte.
GENERAL CONFIGURATION COMMANDS
COMMAND NAME
CMD CODE DESCRIPTION
TYPE
PAGED
DATA
FORMAT UNITS
NVM
DEFAULT
VALUE
MFR_CHAN_CONFIG
0xD0
Configuration bits that are channel-specific
R/W Byte
Y
Reg
Y
0x1D
MFR_CONFIG_ALL
0xD1
General configuration bits
R/W Byte
N
Reg
Y
0x21
MFR_CHAN_CONFIG
General-purpose configuration command common to multiple ADI products.
BIT
MEANING
7
Reserved
6
Reserved
5
Reserved
4
Disable RUN Low. When asserted, the RUN pin is not pulsed low if commanded Off.
3
Enable Short Cycle recognition if this bit is set to a 1.
2
SHARE_CLOCK control. If SHARE_CLOCK is held low, the output is disabled.
1
No FAULT ALERT, ALERT is not pulled low if FAULT is pulled low externally. Assert this bit if either POWER_GOOD or VOUT_UVUF are
propagated on FAULT.
0
Disables the VOUT decay value requirement for MFR_RETRY_TIME and tOFF(MIN) processing. When this bit is set to a 0, the output must
decay to less than 12.5% of the programmed value for any action that turns off the rail, including a fault, an Off/On command, or a toggle
of RUN from high to low to high.
This command has one data byte.



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