LTM4673 datasheet(41/132 Pages) AD

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LTM4683

Rev. 0

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OPERATION

DEVICE ADDRESSING

The LTM4683 offers five different types of addressing

over the PMBus interface, specifically: 1) global, 2) device,

3) rail addressing and 4) alert response address (ARA).

Global addressing provides a means for the PMBus main

device to address all LTM4683 devices on the bus. The

LTM4683 global address is fixed 0x5A (7-bit) or 0xB4

(8-bit) and cannot be disabled. Commands sent to the

global address act the same as if PAGE is set to a value

of 0xFF. Commands sent are written to both channels

simultaneously. Global command 0x5B (7-bit) or 0xB6

(8-bit) is paged and allows channel-specific command of

all LTM4683 devices on the bus. Other Analog Devices

ICs may respond at one or both of these global addresses.

Reading from global addresses is strongly discouraged.

Device addressing provides the standard means of the

PMBus main device communicating with a single instance

of an LTM4683. The value of the device address is set by

a combination of the ASEL_nn configuration pin and the

MFR_ADDRESS command. When this addressing means

is used, the PAGE command determines the channel being

acted upon. Device addressing can be disabled by writing

a value of 0x80 to the MFR_ADDRESS.

Rail addressing provides a means for the bus main device to

simultaneously communicate with all channels connected

together to produce a single output voltage (PolyPhase).

While similar to global addressing, the rail address can be

dynamically assigned with the paged MFR_RAIL_ADDRESS

command, allowing for any logical grouping of channels

that might be required for reliable system control. Reading

from rail addresses is also strongly discouraged.

All four means of PMBus addressing require the user to

employ disciplined planning to avoid addressing conflicts.

Communication to LTM4683 devices at global and rail

addresses should be limited to command write operations.

RESPONSES TO VOUT AND IIN/IOUT FAULTS

VOUT OV and UV conditions are monitored by com-

parators. The OV and UV limits are set in the following

three ways.

As a Percentage of the VOUT if Using the Resistor

Configuration Pins

In NVM, if Either Programmed at the Factory or

Through the GUI

By PMBus Command

The IIN and IOUT overcurrent monitors are performed by

ADC readings and calculations. Thus, these values are

based on average currents and can have a time latency

of up to tCONVERT. The IOUT calculation accounts for the

DCR and their temperature coefficient. The input current

equals the voltage measured across the RSENSEn resis-

tor divided by the resistor value as set with the MFR_

IIN_CAL_GAIN command. If this calculated input current

exceeds the IN_OC_WARN_LIMIT, the ALERT_nn pin is

pulled low, and the IIN_OC_WARN bit is asserted in the

STATUS_INPUT command.

The digital processor within the LTM4683 provides the

ability to ignore the fault, shut down and latch off, or shut

down and retry indefinitely (hiccup). The retry interval

is set in MFR_RETRY_DELAY and can be from 120ms

to 83.88 seconds in 10µs increments. The shutdown for

OV/UV and OC can be done immediately or after a user-

selectable deglitch time.

Output Overvoltage Fault Response

A programmable overvoltage (OV) comparator guards

against transient overshoots and long-term overvoltages

at the output. In such cases, the top MOSFET is turned off,

and the bottom MOSFET is turned on. However, the reverse

output current is monitored while the device is in OV fault.

When it reaches the limit, both top and bottom MOSFETs

are turned off. The top and bottom MOSFETs will keep their

state until the overvoltage condition is cleared, regardless

of the PMBus VOUT_OV_FAULT_RESPONSE command

LTM4673 Datasheet(PDF) 41 Page - Analog Devices

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