LTM4673 datasheet(67/132 Pages) AD

67 / 132 page

LTM4683

Rev. 0

For more information www.analog.com

APPLICATIONS INFORMATION

relative to PMBus timing. If the part is busy process-

ing a command, and new command(s) arrive, execution

may be delayed or processed in a different order than

received. The part indicates when internal calculations

are in process through bit 5 of MFR_COMMON (“calcu-

lations not pending”). When the part is busy calculating,

bit 5 is cleared. When this bit is set, the part is ready for

another command. An example polling loop is provided in

Figure 33, which ensures that commands are processed

in order while simplifying error-handling routines.

// wait until chip is not busy

{

mfrCommonValue = PMBUS_READ_BYTE(0xEF);

partReady = (mfrCommonValue & 0x68) == 0x68;

}while(!partReady)

// now the part is ready to receive the next

command

PMBUS_WRITE_WORD(0x21, 0x2000); //write VOUT_

COMMAND to 2V

Figure 33. Example of a Command Write of VOUT_COMMAND

When the part receives a new command while busy, it will

communicate this condition using standard PMBus pro-

tocol. Depending on the part configuration, it may either

NACK the command or return all ones (0xFF) for reads.

It may also generate a BUSY fault and ALERT notifica-

tion, or stretch the SCL clock low. For more information,

refer to PMBus Specification v1.1, Part II, Section 10.8.7

and SMBus v2.0, section 4.3.3. Clock stretching can be

enabled by asserting bit 1 of MFR_CONFIG_ALL. Clock

stretching will only occur if enabled, and the bus com-

munication speed exceeds 100kHz.

PMBus busy protocols are well-accepted standards, but

can make writing system-level software somewhat com-

plex. The part provides three “hand shaking” status bits,

which reduce complexity while enabling robust system-

level communication.

The three hand shaking status bits are in the MFR_

COMMON register. When the part is busy executing an

internal operation, it will clear bit 6 of MFR_COMMON

(“chip not busy”). When the part is busy specifically

because it is in a transitional VOUT state (margining hi/lo,

power off/on, moving to a new output voltage set point,

etc.), it will clear bit 4 of MFR_COMMON (“output not in

transition”). When internal calculations are in process,

the part will clear bit 5 of MFR_COMMON (“calculations

not pending”). These three status bits can be polled with

a PMBus read byte of the MFR_COMMON register until

all three bits are set. A command immediately following

the status bits being set will be accepted without NACKing

or generating a BUSY fault/ALERT notification. The part

can NACK commands for other reasons, however, as

required by the PMBus spec (for instance, an invalid com-

mand or data). An example of a robust command write

algorithm for the VOUT_COMMAND register is provided

in Figure 33.

It is recommended that all command writes (write byte,

write word, etc.) be preceded with a polling loop to avoid

the extra complexity of dealing with busy behavior and

unwanted ALERT notification. A simple way to achieve this

is to create a SAFE_WRITE_BYTE() and SAFE_WRITE_

WORD() subroutine. The above polling mechanism allows

your software to remain clean and simple while robustly

communicating with the part. For a detailed discussion of

these topics and other special cases, refer to the Analog

Devices Application Note section.

When communicating using bus speeds at or below

100kHz, the polling mechanism shown here provides a

simple solution that ensures robust communication with-

out clock stretching. At bus speeds in excess of 100kHz,

it is strongly recommended that the part be configured

to enable clock stretching. This requires a PMBus main

device that supports clock stretching. System software

that detects and properly recovers from the standard

PMBus NACK/BUSY faults as described in the PMBus

Specification v1.1, Par II, Section 10.8.7 is required to

communicate. The LTM4683 is not recommended in

applications with bus speeds in excess of 400kHz.

THERMAL CONSIDERATIONS AND OUTPUT

CURRENT DERATING

The thermal resistances reported in the Pin Configuration

section of this data sheet are consistent with those

parameters defined by JESD51-12 and are intended for

use with finite element analysis (FEA) software model-

ing tools that leverage the outcome of thermal model-

ing, simulation, and correlation to hardware evaluation

LTM4673 Datasheet(PDF) 67 Page - Analog Devices

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