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RT600 Datasheet(PDF) 114 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 114 Page - NXP Semiconductors |
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114 / 171 page ![]() RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2024. All rights reserved. Product data sheet Rev. 2.2 — 25 January 2024 114 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs 14.10 USART interface Excluding delays introduced by external device and PCB, the maximum supported bit rate for USART master synchronous mode is 20 Mbit/s, and the maximum supported bit rate for USART slave synchronous mode is 20.0 Mbit/s. Excluding delays introduced by external device and PCB, the maximum bit rates of 6.25 Mbit/s in asynchronous mode. The actual USART bit rate depends on the delays introduced by the external trace, the external device, system clock (CCLK), and capacitive loading. [1] Based on simulation; not tested in production. Table 42. USART dynamic characteristics[1] Tamb = 0 C to 85C; VDDIO_x = 1.71 V to 3.6 V; CL = 10, VDDCORE = 1.13 V pF balanced loading on all pins; Full Drive Mode on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 50 % level of the rising or falling edge. Symbol Parameter Conditions Min Typ Max Unit USART master (in synchronous mode) tsu(D) data input set-up time 12.0 - - ns th(D) data input hold time 12.0 - - ns tv(Q) data output valid time -5.0 - 10.0 ns USART slave (in synchronous mode) tsu(D) data input set-up time 8.0 - - ns th(D) data input hold time 0 - - ns tv(Q) data output valid time 0 - 20.0 ns Fig 13. USART timing Un_SCLK (CLKPOL = 0) TXD RXD Tcy(clk) tsu(D) th(D) tv(Q) START BIT0 tvQ) Un_SCLK (CLKPOL = 1) START BIT0 BIT1 BIT1 aaa-015074 |
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