RT600 datasheet(121/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

121 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

14.13

FlexSPI flash interface

Table 45. Dynamic characteristics: FlexSPI flash interface [1]

Tamb = 0 C to +85 C, VDDIO_x = 1.71 V to 1.89 V; VDDCORE = 1.13 V; CL = 10 pF balanced loading on all pins; Full Drive

Mode on all pins, Input slew = 1 ns, SLEW setting = standard mode for all pins; Parameters sampled at the 50 % level of the

rising or falling edge.

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

SDR Mode (FlexSPI A Interface)

fclk

clock frequency

Transmit

200

MHz

clock frequency

RX clock source = 0

MHz

clock frequency

RX clock source = 1

116

MHz

clock frequency

RX clock source = 3

200

MHz

tDS

data set-up time

RX clock source = 0 (internal

dummy read strobe and

loopbacked internally)

RX clock source = 1 (internal

dummy read strobe and

loopbacked from DQS pad)

source = 3 (external DQS,

Flash provides read strobe)

tDH

data hold time

RX clock source = 0 (internal

dummy read strobe and

loopbacked internally)

RX clock source = 1 (internal

dummy read strobe and

loopbacked from DQS pad)

source = 3 (external DQS,

Flash provides read strobe)

tv(Q)

data output valid time

SDR Mode (FlexSPI B Interface)

fclk

clock frequency

Transmit

MHz

clock frequency

RX clock source = 0

MHz

clock frequency

RX clock source = 1

MHz

tDS

data set-up time

RX clock source = 0 (internal

dummy read strobe and

loopbacked internally)

RX clock source = 1 (internal

dummy read strobe and

loopbacked from DQS pad)

tDH

data hold time

RX clock source = 0 (internal

dummy read strobe and

loopbacked internally)

RX clock source = 1 (internal

dummy read strobe and

loopbacked from DQS pad)

tv(Q)

data output valid time

DDR Mode (with and without DQS) (FlexSPI A Interface) [2]

fclk

clock frequency

Transmit

200

MHz

clock frequency

RX clock source = 0

MHz

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