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RT600 Datasheet(PDF) 131 Page - NXP Semiconductors |
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RT600 Datasheet(HTML) 131 Page - NXP Semiconductors |
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131 / 171 page  RT600 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors B.V. 2024. All rights reserved. Product data sheet Rev. 2.2 — 25 January 2024 131 of 173 NXP Semiconductors RT600 Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4 Audio DSP CPUs [1] Based on simulation, not tested in production. [1] Based on simulation, not tested in production. [2] When communication with an I3C Device on a mixed Bus, the tDIG_H period must be constrained in order to make sure that I2C devices do not interpretI3C signaling as valid I2C signaling. Table 54. MIPI I3C push-pull specifications for SDR and HDR-DDR modes [] Symbol Characteristic Min Typ Max Unit Notes fSCL SCL Clock Frequency 0.01 12.5 13 MHz tLOW LOW period of the SCL clock 24 - - ns tDIG_L 32 - - ns tHIGH_MIX ED High period of the SCL clock for a mixed bus 24 - - ns tDIG_H_MI XED 32 - 45 ns [] tHIGH HIGH period of the SCL clock 24 - - ns tDIG_H 32 - - ns tSCO Clock in to data out for a slave - - 12 ns tCR SCL clock rise time - - 150e06 * 1/ fSCL (capped at 60) ns tCF SCL clock fall time - - 150e06 * 1/ fSCL (capped at 60) ns tHD_PP SDA signal data hold Master mode tCR + 3 and tCF + 3 - - ns Slave mode 0 - - ns tSU_PP SDA signal setup 3 - - ns tCASr Clock after repeated START (Sr) tCAS(min)/2 - - ns tCBSr Clock before repeated START (Sr) tCAS(min)/2 - - ns Cb Capacitive load per bus line - - 50 pF Fig 27. Timing definition for devices on the I2C bus |
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