RT600 datasheet(132/171 Pages) NXP

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RT600

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Product data sheet

Rev. 2.2 — 25 January 2024

132 of 173

NXP Semiconductors

RT600

Dual-core microcontroller with 32-bit Cortex-M33 and Xtensa HiFi4

Audio DSP CPUs

15. Analog characteristics

15.1 12-bit ADC characteristics

[1] Based on characterization; not tested in production.

[2] Typical ratings are not guaranteed. The values listed are at room temperature (25 C), nominal supply

voltages.

[3] CADIN represents the external capacitance on the analog input channel for sampling speeds of

1.0 Msamples/s. No parasitic capacitances included. See Figure 29

[4] The differential linearity error (ED) is the difference between the actual step width and the ideal step width.

See Figure 28.

[5] The integral non-linearity (EL(adj)) is the peak difference between the center of the steps of the actual and

the ideal transfer curve after appropriate adjustment of gain and offset errors. See Figure 28.

[6] The offset error (EO) is the absolute difference between the straight line which fits the actual curve and the

straight line which fits the ideal curve. See Figure 28.

[7] The full-scale error voltage or gain error (EG) is the difference between the straight-line fitting the actual

transfer curve after removing offset error, and the straight line which fits the ideal transfer curve. See

Figure 28.

[8] This resistance is external to the MCU. To achieve the best results, the analog source resistance must be

kept as low possible. The results in this data sheet were derived from a system that had < 15 Ω analog

source resistance. See Figure 29.

Table 55. 12-bit ADC static characteristics

Tamb = -20 C to +85 C; VDD_AO1V8 = 1.8 V, VDD1V8 = 1.8 V, VDDIO_0/1/2 = 1.8 V, VDDA_ADC1V8 = VDDA_BIAS =

VREFP = 1.8 V; VSSA = VREFN = GND. fclk(ADC) = 22 MHz; Sample Time select (STS bit in CMDH register) = 0.

Symbol

Parameter

Conditions

Min

Typ[2]

Max

Unit

VADIN

analog input

voltage

See

Figure 29 VREFN -

VREFP

fclk(ADC)

ADC clock

frequency

MHz

sampling

frequency

1.0

Msamples/s

Csamples

Sample cycles

3.5

131.5

Ccompare

Fixed compare

cycles

17.5

cycles

Cconversion Conversion cycles

Cconversion = Csamples + Ccompare cycles

CADIN

Analog Input

Capacitance

[3]

See

Figure 29.

4.5

RADIN

Input Resistance

See

Figure 29. -

500

RAS

Analog source

resistance

[8]

See

Figure 29

kΩ

differential linearity

error

[1][4] -



LSB

EL(adj)

integral

non-linearity

[1][5] -



1.1

LSB

offset error

[1][6] -



LSB

Verr(FS)

full-scale error

voltage

[1][7] -



0.3

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