 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ADPD7008 Datasheet(PDF) 6 Page - Analog Devices |
|
|
|||||||||||||||||||||||||||||
ADPD7008 Datasheet(HTML) 6 Page - Analog Devices |
|
|
6 / 71 page  Data Sheet ADPD7008 SPECIFICATIONS analog.com Rev. 0 | 6 of 71 TIMING SPECIFICATIONS Table 4. Timing Specifications Parameter Symbol Test Condition/Comments Min Typ Max Unit SPI PORT SCLK Frequency fSCLK 10 MHz Minimum Pulse Width High tSCLKPWH 15 ns Low tSCLKPWL 15 ns CS Setup Time tCSS CS setup to SCLK rising edge 11 ns Hold Time tCSH CS hold from SCLK rising edge 5 ns Pulse Width High tCSPWH CS pulse width high 15 ns MOSI Setup Time tMOSIS MOSI setup to SCLK rising edge 5 ns Hold Time tMOSIH MOSI hold from SCLK rising edge 5 ns SWITCHING CHARACTERISTICS MISO Output Delay tMISOD MISO valid output delay from SCLK falling edge Register 0x057 = 0x0050 (default) 21.5 ns Register 0x057 = 0x005F (maximum slew rate, maximum drive strength for SPI) 14 ns Timing Diagram Figure 2. SPI Timing Diagram |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
English ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
