ADPD7008 datasheet(17/71 Pages) AD

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Data Sheet

ADPD7008

THEORY OF OPERATION

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Table 11. OP_MODE Bit Setting Descriptions (Continued)

OP_MODE Setting Mode

Description

011

ADC test

mode

This mode goes through the normal wake-up

sequence and then does continuous ADC

cycles based on the PPG Time Slot A setting

101

Repeat

selected

time slots

without

sleep

This mode does one normal wake-up

sequence and then cycles through the enabled

time slot sequences without going to sleep

between.

111

Reserved

Reserved.

At power-up and following any subsequent reset operations, the

ADPD7008 is in standby mode. The user can write 0 to the

OP_MODE bit to immediately stop operations and return to standby

mode.

The time slots are enabled by the PPG_TIMESLOT_EN bit in the

OPMODE register (see Register 0x010 in Table 15).

Set PPG_TIMESLOT_EN to a certain value to enable the corre-

sponding PPG time slot.

After enabling the desired time slots, set the OP_MODE bit to 1 to

start the chip operation.

go mode. The user must enter standby mode before changing the

control registers. Standby mode resets the digital portion of the

ADC, all of the pulse generators, and the state machine.

When OP_MODE is set to 1, the device immediately starts the first

wake-up sequence and time slot operations unless using an exter-

nal synchronization trigger. If using an external synchronization

trigger, the device enters the sleep state before the first wake-up

and time slot regions begin.

HOST INTERFACE

The ADPD7008 uses an SPI to communicate with other devices.

The device also provides numerous FIFO, error, and threshold

status bits, each of which can be provided by an interrupt function

from a GPIO, read from status registers, or appended as optional

status bytes at the end of a FIFO packet.

Interrupt Status Bits

FIFO Threshold Interrupt

The FIFO threshold interrupt status bit, INT_FIFO_TH, is set when

the number of bytes in the FIFO exceeds the value stored in the

FIFO_TH register. The INT_FIFO_TH bit is cleared automatically

when a FIFO read reduces the number of bytes below the value in

the FIFO_TH register, which allows the user to set an appropriate

data size for their host needs.

The INT_FIFO_TH bit does not trigger if the FIFO byte count

exceeds the threshold in the middle of any write of complete data.

Instead, the INT_FIFO_TH bit is set at the next write to the FIFO.

For example, if only PPG TSA is running, it only writes 4-byte lit

data to the FIFO. Figure 18 shows the data in the FIFO.

Figure 18. FIFO Threshold Interrupt Example

If the threshold is set as 4, the interrupt triggers at the beginning of

the second TSA data write to the FIFO. If the threshold is set as 5,

6, or 7, the INT_FIFO_TH bit does not trigger until the write of the

third TSA data. This method can help prevent any partial data read

from the FIFO.

Clearing Interrupt Status Bits

All status bits are set regardless of whether the status bit is routed

to one of the interrupt outputs, Interrupt X or Interrupt Y. The status

bits are independent of the interrupt enable bits. The status bits are

always set by the corresponding event. The interrupt bits stay set

until they are either manually or automatically cleared.

The user can manually clear a given interrupt by writing a 1 to

the matching interrupt status bit. In addition, the data interrupt

status bits can be configured to clear automatically. When the

INT_ACLEAR_FIFO bit is set, the appropriate interrupt status bit

is automatically cleared when any matching FIFO register is read.

Automatic clearing of the interrupt status bits removes the need to

manually clear these interrupts.

Optional Status Bytes

There is an option to append each data packet with status bits. This

option is useful for hosts that cannot spare an interrupt channel

to service. The status bytes can each be individually selected

in the FIFO_STATUS_BYTES register. Each bit in the FIFO_ STA-

TUS_BYTES register enables a status byte that is appended to the

data packet in the FIFO. If any bit in the FIFO_STATUS_ BYTES

contains the status bits.

The 4-bit sequence number cycles from 0 to 15 and is incremented

with a wraparound every time the time slot sequence completes.

This sequence number can also be made available bitwise on the

GPIOx pins.

Interrupt Outputs, Interrupt X and Interrupt Y

The ADPD7008 supports two separate interrupt outputs, Interrupt X

and Interrupt Y. Each interrupt has the option to be driven to any

of the two GPIOx pins. The two different interrupt outputs can be

generated for a host processor if desired. For example, the FIFO

threshold interrupt, INT_FIFO_TH, can be routed to Interrupt X and

used to drive the direct memory access (DMA) channel of the host,

while the INT_FIFO_OFLOW and INT_FIFO_UFLOW interrupts

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