ADPD7008 datasheet(18/71 Pages) AD

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Data Sheet

ADPD7008

THEORY OF OPERATION

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can be routed to Interrupt Y and used to drive an additional host

interrupt pin.

For each interrupt, there is an associated Interrupt X and Interrupt

Y enable bit. See Table 16 for a full list of available interrupts that

can be brought out on Interrupt X and Interrupt Y. The logic for the

Interrupt X and Interrupt Y function is a logic AND of the status

bit with its matching enable bit. All enabled status bits are then

logically OR’ed to create the interrupt function. The enable bits do

not affect the status bits.

General-Purpose I/Os

The ADPD7008 provides two general-purpose I/O pins: GPIO0 and

GPIO1. These GPIOs can be used as previously described in the

Interrupt Outputs, Interrupt X and Interrupt Y section for interrupt

outputs or for providing external clock signals to the device. The

GPIOs can also be used for many different control signals, as

synchronization controls to external devices, as well as test signals

that are useful during system debugging. All of the available signals

that can be brought out on a GPIOx pin are listed in Table 16.

IOVDD Supply Voltage Consideration

The ADPD7008 can operate with IOVDD as low as 1.7 V and as

high as 3.6 V. LOW_IOVDD_EN in Register 0x0057 is set to 0x1 for

IOVDD lower than 3 V. 0x1 is the default value for this bit because

the typical IOVDD value is 1.8 V.

If 3 V or higher is supplied for IOVDD, the LOW_IOVDD_EN bit

must be set to 0x0 for proper operation.

SPI

The ADPD7008 contains an SPI port that operates synchronously

with its input clocks.

The ADPD7008 has an internal power-on reset circuit that sets the

device into a known idle state during the initial power-up. After the

power-on reset is released, approximately 2 µs to 6 μs after the

DVDD supply is active, there is an initialization state that sets the

15 µs to 20 µs. The device can then be read and written through

the SPI.

The registers are accessed using addresses within a 15-bit address

space. Each address references a 15-bit register with one address

reserved for the FIFO read accesses. For SPIs, reads and writes

auto-increment to the next register if additional words are accessed

as part of the same access sequence. This automatic address

increment occurs for all addresses except the FIFO address, one

less than the FIFO address and the last used address, which is

0x351. Reads from the FIFO address continue to access the next

byte from the FIFO.

SPI Operations

The SPI single register write operation is shown in Figure 19. The

first two bytes contain the 15-bit register address and specify that a

write is requested. The remaining two bytes are the 16 data bits to

write to the register. The register write occurs only when all 16 bits

are shifted in prior to deassertion of the CS signal.

In addition, multiple registers can be written if additional 16-bit

data is shifted in before deassertion of the CS signal. The register

address automatically increments to the next register after each 16

bits of data.

The SPI single register read operation is shown in Figure 20. The

first two bytes contain the 15-bit register address and specify that

a read is requested. Register bits are shifted out starting with the

MSB. In addition, multiple registers can be read if additional 16-bit

data is shifted out prior to deassertion of the CS signal.

It is recommended that reading from the FIFO is performed byte

wise. There is no requirement to read multiples of 16 bits.

Figure 19. SPI Write Operation

Figure 20. SPI Read Operation

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