ADPD7008 datasheet(22/71 Pages) AD

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Data Sheet

ADPD7008

APPLICATIONS INFORMATION

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Rev. 0 | 22 of 71

Figure 25. Timing of OSRAM FIREFLY CT DBLP31.12 (Green LED)

DESIGN GUIDE

The ADPD7008 is a vital sign monitoring AFE. The performance of

the device can be adversely impacted by the PCB layout, especially

for the analog input interfaces.

Power Rails

For the power supply, decouple the AVDD, AVDD3, DVDD, and

IOVDD pins with a 0.1 μF or larger ceramic chip capacitor to the

PCB ground plane placed near the power pins. It is recommended

that all decoupling capacitors use individual vias to the PCB ground

plane to avoid mutual impedance coupling between decoupled

supplies when sharing vias.

Optical Channel

For the PPG channel, decouple the VREF1 pin and VREF2 pin to

the PCB ground plane with a 1.0 μF ceramic capacitor. The voltage

on the VREF1 pin and VREF2 pin is nominally 1.2 V. Therefore,

a 6.3 V rated ceramic capacitor is adequate for this purpose. The

most critical aspect of the PCB layout of the ADPD7008 is the

handling of the IN1, IN2, IN3, and IN4 nodes. Because photodiode

input is sensitive to noise, and any parasitic capacitive coupling to

the pin can result in additional noise, it is recommended that the

photodiode input trace in the layout be as short as possible and

fully guarded by the ground plane.

For example, for a 6-layer stack design, place the chip in the top

layer with the optical components in the bottom layer. Therefore, it

is recommended to make the IN1, IN2, IN3, and IN4 trace length

in the top short to avoid parasitic effects. In the bottom layer, the

IN1, IN2, IN3, and IN4 traces and the photodiode anode are fully

guarded with the ground shape and trace. VC1 and the photodiode

cathode are also guarded with the ground plane. Layer 5 is filled

with a ground plane for reference. Keep the analog input signals

away from other digital or noisy signals.

ADPD7008 Datasheet(PDF) 22 Page - Analog Devices