ADPD7008 datasheet(19/71 Pages) AD

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Data Sheet

ADPD7008

APPLICATIONS INFORMATION

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OPTICAL PATH

Digital Integration Mode

The ADPD7008 supports a digital integration mode in the optical

path to accommodate sensors that require longer pulses. Digital

integration mode allows the system to use a larger LED duty cycle,

which can result in the highest achievable SNR levels.

Figure 21. Signal Path for Digital Integration Mode

In digital integration mode, the integrator is configured as a buffer,

resulting in the signal path shown in Figure 21. Digital integration

regions are configured by the user and separated into lit and dark

regions. The LED is pulsed in the lit region, and the LED is off in

the dark region. ADC samples are taken at 1 μs intervals within the

lit and dark regions and are then digitally integrated. The integration

of the ADC samples from the dark region is subtracted from the

integration of the ADC samples from the lit region, and the result is

written into the relevant FIFO. Both signal and dark values can be

written to the FIFO.

The ADPD7008 supports one-region and two-region digital integra-

tion modes. In one-region digital integration mode, an equal number

of dark and lit samples are taken where all of the dark samples are

taken in the dark region just before the lit region. One-region digital

integration mode is shown in the timing diagram in Figure 22.

In two-region digital integration mode, an equal number of dark

and lit samples are taken. However, the dark region is split such

that half of the samples are taken in the dark region before the lit

region, and the other half is taken in the dark region following the

lit region. The two-region digital integration mode results in higher

ambient light rejection than the one-region digital integration mode

in situations with a varying ambient light level. A timing diagram for

two-region digital integration mode is shown in Figure 23.

The signal data for one-region digital integration mode that reads

from the FIFO follows:

Signal= IPD×RTIA×TIA_CONFIG×BUF

_GAIN×NUM_INT_x×NUM_REPEAT_x/

146 μV/LSB

(2)

where:

IPD is the PD current.

TIA_CONFIG is the TIA configuration. BUF_GAIN is the buffer gain.

The signal data for two-region digital integration mode that reads

from the FIFO follows:

Signal= IPD×RTIA×TIA_CONFIG×BUF

_GAIN×NUM_INT_x×NUM_REPEAT_x/

146 μV/LSB ×2

(3)

The AFE_PATH_CFG_x, TIA_GAIN_CHx_x, AFE_BUF-

FER_GAIN_x, and AFE_BUFFER_CAP_x bits must follow a certain

combination in digital integration mode (both one-region mode and

two-region mode). Table 12 shows the recommended settings of

these bits. The TIA gain setting is independent of these settings.

Table 12. Bit Settings for AFE Path in Digital Integration Mode

Bit Name

Recommended Setting

AFE_PATH_CFG_x

0x28

TIA_GAIN_CHx_x

0x3

AFE_BUFFER_GAIN_x

0x3

AFE_BUFFER_CAP_x

0x1

The result of the configurations of the bits in Table 12 is the 1× TIA

configuration with a buffer gain = 2.

Table 13 shows the relevant register settings for the digital integra-

tion modes of operation. The MIN_PERIOD_x bits must be set

manually with the proper period because the minimum period is not

automatically calculated in digital integration mode.

The recommended MIN_PERIOD_x setting for one-region digital

integration mode is as follows:

MIN_PERIOD_x=NUM_INT_x×2+ 2+tD ×2

The recommended MIN_PERIOD_x setting for two-region digital

integration mode is as follows:

MIN_PERIOD_x=NUM_INT_x×4+tD×2+6 μs

The tD value is the response time of the optical device. The 6 μs

time is essential for the ambient fine loop update.

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