ADPD7008 datasheet(12/71 Pages) AD

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Data Sheet

ADPD7008

THEORY OF OPERATION

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Rev. 0 | 12 of 71

INTRODUCTION

The ADPD7008 is a vital signal monitoring AFE that comprises an

optical measurement path (PPG) measurement path.

The PPG measurement path works as a transceiver that supports

up to eight LEDs and four photodiode inputs. The current on the

LEDs is programmable from two 7-bit LED drivers. The receiver

path provides two high performance readout channels that can

sample simultaneously and can be configured separately. Two

high performance current DACs (IDACs) are implemented in each

channel to provide first class ambient light suppression and large

dynamic range in different application scenarios.

An internal state machine allows flexible control of this measure-

ment path. The acquisition data can be stored in a 704-byte FIFO.

TIME SLOT OPERATION

An internal configurable controller handles the operation of the

ADPD7008. This controller generates the timing needed to gener-

ate sampling regions comprising combinations of the three meas-

urement paths and sleep periods. To facilitate the use of multiple

signal chains, multiple time slots handle the access to different

transmitters or receivers.

The system is characterized by the ODR, which determines the

repetition periodicity of each enabled time slot. The enabled time

slots are repeated at the time slot rate configured by the TIME-

SLOT_PERIOD_x bits.

There are 12 time slots (PPG_TSA to PPG_TSL) in the ADPD7008,

as shown in Figure 14.

Each PPG time slot allows the creation of one or more LED pulses

and modulate pulses, as well as the acquisition of the photodiode

or other device current based on that stimulus. The operating

parameters for each time slot are highly configurable.

Equation 1 determines the sampling rate (time slot rate), as follows:

Sampling

Rate

=Timer

Clock Frequency (Hz)

/TIMESLOT_PERIODx

(1)

Table 9. Sources of Low Frequency Clock (LFCLK) and Timer Clock1

LFCLK

Timer Clock

ALT_CLOCKS TM_CLK_GPIO_SEL

960 kHz Internal

960 kHz internal 0

N/A

960 kHz External

960 kHz external 1

N/A

960 kHz Internal

960 kHz internal 2

N/A

1 MHz External

(Divided from 32

MHz)

1 MHz external

(divided from 32

MHz)

N/A

960 kHz Internal

960 kHz external 4

960 kHz Internal

32 kHz external

1 N/A means not applicable.

Figure 14. Time Slot Allocation

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