STPMIC25 datasheet(55/145 Pages) STMICROELECTRONICS

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Figure 19. Thermal protection thresholds

Tj°

TWRN_Rise

THW_RI Interrupt

THW_FA Interrupt

TSHDN_Rise

TWRN_Fall

TSHDN_Fall

5.4.9

Overcurrent (OCP) and Hiccup mode

All regulators implement protection against overcurrent (OC) on their output.

Note:

Short-circuits (SC) are managed by the overcurrent protection.

For each regulator, the PMIC embeds 2 levels of protection against overcurrent and short-circuits:

•

Level 0 (default): independent regulator OCP Hiccup mode management

•

Level 1: PMIC OCP fail-safe management (see Section 5.4.5)

•

The default level of protection is defined in the NVM (NVM_FS_OCP_SHR1/2) for each regulator, and can

be changed at runtime by software (FS_OCP_CR1/2)

5.4.9.1

Level 0: independent regulator OCP Hiccup mode management

Each PMIC regulator operates independently in Hiccup mode:

•

When a short-circuit or an overcurrent occurs, the output current is limited to ILDOLIM (for LDO) and IBKLIM

(for buck).

•

If the SC or OC lasts more than tOCPDB_LDO or tOCPDB_BUCK (respectively for LDO or buck):

–

The regulator turns OFF for the tHICCUP_DLY duration

–

An interrupt is generated (if the interrupt is unmasked by software)

•

Once the tHICCUP_DLY timer elapses, the regulator turns ON

–

If the SC or OC is removed, the LDO operates normally

–

If the SC or OC stays present, the regulator goes into step 1, repeating the cycle until the overload

disappears (hiccup)

Notes:

•

1) When the tHICCUP_DLY timer duration is set to 0, the regulator is turned-OFF (interrupt-generated) and it

does not restart (step 3 is skipped).

•

2) The tHICCUP_DLY timer duration can be adjusted in the NVM by setting the HICCUP_DLY[1:0] bit field in

the NVM_BUCKS_IOUT_SHR2 shadow register then programming the NVM.

•

3) The tHICCUP_DLY timer is reset if a POWER_DOWN occurs at the same time. In this way, the IP can

restart with its assigned RANK at the next POWER_UP. This happens even if the mask reset is set and/or

tHICCUP_DLY is set to ‘0’.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 55/145

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