STPMIC25 datasheet(26/145 Pages) STMICROELECTRONICS

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4.2

LDO regulators

LDO1 is a fixed 1.8 V low drop linear regulator designed to be typically used to supply the VDDA18AON MPU

application domain that needs to be powered.

LDO2, LDO5, LDO6, LDO7, and LDO8 are general purpose LDOs suitable to supply MPU application peripherals.

All these LDOs are provided with a bypass mode function.

LDO3 serves for DDR3, DDR3L, DDR4 memory termination (sink-source mode) or to support the general

purpose mode or bypass mode, which is typically suitable for supplying lpDDR's 1.8 V power domain.

LDO4 is a fixed 3.3 V regulator designed to supply a 3V3 USB PHY circuit. It has two voltage sources (VIN or

VBUS) which allows the LDO4 output voltage to stay at 3.3 V when VIN is powered by a discharged battery < 3.3 V

and VBUS powered by 5 V.

VREFDDR is a sink-source reference voltage dedicated for lpDDR/DDR.

4.2.1

Common features

Enable/disable - each LDO can be enabled or disabled independently:

•

Automatically during the POWER_UP or POWER_DOWN sequence depending on the NVM settings.

•

By software (I2C access): setting the EN bit in the related LDO control register.

•

By PWRCTRLx pins state change: the PWRCTRLx pins need to be programmed by I2C to enable this

feature.

VLDOOUT voltage setting - LDO output voltage can be set:

•

Automatically during the POWER_UP or POWER_DOWN sequence depending on the NVM settings.

•

By software (I2C access): setting the VOUT bit field in the related LDO control register.

•

By PWRCTRLx pins state change: the PWRCTRLx pins need to be programmed by I2C to select the

output voltages needed to meet the MPU application requirements.

Bypass mode operation - this mode is set by the BYPASS bit in the related LDO control register:

When in bypass mode, the LDO operates as a power switch allowing voltage to bypass from the VLDOIN to the

VLDOOUT of a corresponding LDO. The LDO can be enabled or disabled as in normal operation. See the “Enable/

disable” description above.

Soft-start: this feature aims to limit input inrush current during the LDO startup phase. LDO soft-start duration is

defined by the tSSLDO parameter.

See Figure 3

STPMIC25

Power regulator descriptions

DS14278 - Rev 3

page 26/145

STPMIC25 Datasheet(PDF) 26 Page - STMicroelectronics