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STPMIC25 Datasheet(PDF) 43 Page - STMicroelectronics |
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STPMIC25 Datasheet(HTML) 43 Page - STMicroelectronics |
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43 / 145 page  5.3.2 WAKEUPn Main characteristics: • Digital input • Active low • Programmable pull-up (RPU) internally connected to VINTLDO; RPU active by default • Turn-ON condition on low level (1) • Interrupt on falling and rising edges (1) 1. WAKEUPn has no debounce filter. The PMIC detects a pulse smaller than the tWAKEUPnAS duration. The PMIC must detect a pulse equal to or longer than the tWAKEUPnAS duration. 5.3.3 RSTn The RSTn is a bidirectional reset pin both for the PMIC and the application processor: • Digital input: active low input reset (when not asserted by the PMIC): the application processor can assert RSTn low to force the PMIC to power cycle. • Open drain output: the PMIC can assert RSTn low to reset the application processor, typically during a power-ON or a power-OFF sequence and a power cycling reset sequence. Pull-up (RPU) is internally connected to VIO. 5.3.4 INTn The PMIC asserts INTn low when a PMIC interrupt is pending (and not masked): • Digital output (open drain) • Active low • Pull-up (RPU) internally connected to VIO 5.3.5 PWRCTRL1, PWRCTRL2, PWRCTRL3 Power control signals aim to control the regulator's behavior. Typically, power control signals are driven to ‘1’ or ‘0’ by the application processor to manage different power modes at application level. PWRCTRLx pin characteristics: • Digital input • Level sensitive • Programmable polarity • Rising and falling delay cells • Inactive by default • Programmable pull-up (RPU) internally connected to VIO or pull-down (RPD), and RPU is active by default. • No debounce See Section 5.4.6 for behavior description. STPMIC25 Feature descriptions DS14278 - Rev 3 page 43/145 |
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