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STPMIC25 Datasheet(PDF) 89 Page - STMicroelectronics |
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STPMIC25 Datasheet(HTML) 89 Page - STMicroelectronics |
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89 / 145 page  6.3.14 Mask reset buck control register (BUCKS_MRST_CR) 7 6 5 4 3 2 1 0 REFDDR_MRST BUCK7_MRST BUCK6_MRST BUCK5_MRST BUCK4_MRST BUCK3_MRST BUCK2_MRST BUCK1_MRST R/W R/W R/W R/W R/W R/W R/W R/W • Address: 0x1D • Default: 0x00 • Description: mask reset buck control register. See Section 5.4.7.1. This register is initialized to the default value in the CHECK&LOAD state. [7] REFDDR_MRST: mask reset setting 0: inactive 1: active [6] BUCK7_MRST: mask reset setting 0: inactive 1: active [5] BUCK6_MRST: mask reset setting 0: inactive 1: active [4] BUCK5_MRST: mask reset setting 0: inactive 1: active [3] BUCK4_MRST: mask reset setting 0: inactive 1: active [2] BUCK3_MRST: mask reset setting 0: inactive 1: active [1] BUCK2_MRST: mask reset setting 0: inactive 1: active [0] BUCK1_MRST: mask reset setting 0: inactive 1: active STPMIC25 Register descriptions DS14278 - Rev 3 page 89/145 |
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