STPMIC25 datasheet(56/145 Pages) STMICROELECTRONICS

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5.4.9.2

Level 1: PMIC OCP fail-safe management

Each PMIC regulator can be set independently to trigger a hard-fault condition when an overcurrent or a short

circuit occurs:

•

When a short-circuit or an overcurrent occurs, the output current is limited to ILDOLIM (for LDO) and IBKLIM

(for buck).

•

If the SC or OC lasts more than tOCPDB_LDO or tOCPDB_BUCK (respectively for LDO or buck), the PMIC

generates a turn-OFF hard-fault condition. OCP_SR1 or OCP_SR2 is updated with the OCP fault source,

and the OCP fail-safe counter (1) is incremented (OCP_FLT_CNT ++):

–

If the OCP fail-safe counter reaches the maximum number of power cycles defined in the NVM

(OCP_FLT_CNT > OCP_FLT_CNT_MAX), the PMIC goes in FAIL_SAFE_LOCK state.

–

Alternatively, when the tHICCUP_DLY delay ends, the PMIC restarts.

1. There is a single OCP fail-safe counter (OCP_FLT_CNT) for all regulators. It is incremented each time a regulator triggers a

hard-fault regardless of the regulator instance.

5.4.10

Watchdog management

The PMIC has an internal watchdog timer. A watchdog timer expiration generates a turn-OFF hard-fault condition

(see Section 5.4.4.2 ) followed either by a PMIC restart (power cycling) or by the PMIC going into the

FAIL_SAFE_LOCK state.

The watchdog can be enabled/disabled by software or at power-up (NVM settings), respectively:

•

Software: set/reset WDG_EN bit at runtime

•

NVM: set/reset NVM_WDG_EN bit then program the NVM

The watchdog timer duration can be set in a range from 1 s to 256 s by 1 s step by setting the

WDG_TMR_SET[7:0] bit field. The default watchdog timer duration can be set in the NVM by setting

NVM_WDG_TMR_SET[1:0] then programming the NVM.

Note: Each time the NVM is reloaded (typically in the CHECK&LOAD state), the NVM_WDG_EN bit is copied into

the WDG_EN bit and the NVM_WDG_TMR_SET[1:0] bit field related duration is set into the

WDG_TMR_SET[7:0] bit field. In the POWER_ON state, the software can override the default watchdog values

(NVM) by setting the WDG_EN bit and/or the WDG_TMR_SET[7:0] bit field.

As soon as the watchdog is enabled, the software should periodically set the WDG_RST bit (self-cleared) to

reload the timer downcounter WDG_TMR_CNT[7:0] with the value defined in the WDG_TMR_SET[7:0] bit field.

The software can read the watchdog timer downcounter (WDG_TMR_CNT[7:0]) to check the remaining duration

before expiration.

A turn-OFF hard-fault condition occurs if the watchdog timer expires. The turn-off condition is followed by a

POWER_DOWN sequence either by a PMIC restart (POWER_UP then POWER_ON) or by the PMIC going into

the FAIL_SAFE_LOCK state. (See Section 5.4.5 for details about the behavior following a turn-off hard-fault

event).

Enabling the watchdog (from WDG_EN = 0 to 1) to reload the timer downcounter (WDG_TMR_CNT[7:0]) with the

value defined in the WDG_TMR_SET[7:0] bit field.

When enabled, the watchdog timer remains active in the POWER_ON state (in the RUN or in the STANDBY

state). In all other states, the watchdog timer is frozen.

The watchdog timer can be disabled at runtime by setting WDG_EN = 0. Alternatively, the watchdog timer is

automatically disabled when PMIC goes into the OFF state or the FAIL_SAFE_LOCK state (regardless of turn-

OFF condition source).

When enabled (WDG_EN = 1), the watchdog timer can be suspended automatically from one PWRCTRLx signal.

The WDG_PWRCTRL_SEL[1:0] bit field allows for the selection of the PWRCTRLx source to suspend the

watchdog. It is suitable to automatically suspend/freeze the watchdog when the application is in low power mode:

•

When PWRCTRLx is inactive (the application is running), the watchdog timer downcounter is running. The

software should set the WDG_RST bit periodically to reload the timer downcounter.

•

When PWRCTRLx is active (the application is in low-power mode), the watchdog timer downcounter is

suspended (frozen). When PWRCTRLx becomes inactive (the application leaves the low-power mode), the

watchdog downcounter restarts from the current WDG_TMR_CNT[7:0] value (counter

WDG_TMR_CNT[7:0] is not reloaded from WDG_TMR_SET[7:0] value).

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 56/145

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