STPMIC25 datasheet(98/145 Pages) STMICROELECTRONICS

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6.5.9

LDO1 MAIN mode control register (LDO1_MAIN_CR)

Table 62. LDO1_MAIN_CR

INPUT_SRC

reserved

R/W

•

Address: 0x4C

•

Default: 0b0000000X where X depends on the value programmed in the NVM

•

Description: LDO1 MAIN mode control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control enable LDO1, which is applied to the MAIN mode (see Section 5.4.6.

[7]

INPUT_SRC:

0: LDO12IN as source

1: VOUT4 as source

[6:1] reserved

[0]

EN:

0: LDO1 is disabled

1: LDO1 is enabled

The default value is defined in the LDO1_RANK[2:0] bit field of the NVM_LDOs_RANK_SHR1 NVM shadow registers. If

LDO1_RANK[2:0] = 0, LDO1 is disabled at power up; if LDO1_RANK[2:0] = y (with 6 > y > 0) LDO1 is enabled at power

up at rank y (see Section 5.2)

6.5.10

LDO1 ALTERNATE mode control register (LDO1_ALT_CR)

Table 63. LDO1_ALT_CR

INPUT_SRC

reserved

R/W

•

Address: 0x4D

•

Default: 0b0000000X where X depends on the value programmed in the NVM

•

Description: LDO1 ALTERNATE mode control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control enable LDO1, which is applied to the ALTERNATE mode (see Section 5.4.6.

[7]

INPUT_SRC:

0: LDO12IN as source

1: VOUT4 as source

[6:1]

reserved

[0]

EN:

0: LDO1 is disabled

1: LDO1 is enabled

The default value is the same as LDO1_MAIN_CR

STPMIC25

DS14278 - Rev 3

page 98/145

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