STPMIC25 datasheet(68/145 Pages) STMICROELECTRONICS

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6.2.4

Turn-off status register

Reserved

WDG_FLT

TSHDN_FLT

OCP_FLT

VIN_FLT

PKEY_FLT

SWOFF

•

Address: 0x03

•

Default: 0b00xxxxxx where x depends on the turn-off condition

•

Description: Stores last condition, which turns OFF the PMIC.

The TURN_OFF_SR register is reset in the POWER_DOWN state. Then TURN_OFF_SR is set either when

going into the OFF state or when going into the FAIL_SAFE_LOCK state (see Section 5.4.4 and Section 5.1.2 ).

[7:6]

reserved

[5]

WDG_FLT: Last turn-off is due to watchdog hard-fault source while WDG_FLT_CNT >

WDG_FLT_CNT_MAX.

0: False

1: True

[4]

THSDN_FLT: Last turn-off is due to thermal shutdown hard-fault source while TSHDN_FLT_CNT

> TSHDN_FLT_CNT_MAX.

0: False

1: True

[3]

OCP_FLT: Last turn-off is due to regulator overcurrent hard-fault source while OCP_FLT_CNT >

OCP_FLT_CNT_MAX.

0: False

1: True

[2]

VIN_FLT: Last turn-off is due to VIN falling below VINOK_Fall hard-fault source while

VIN_FLT_CNT > VIN_FLT_CNT_MAX.

(This is valid only if VIN is kept higher than VINPOR_Fall; or the PMIC fully resets)

0: False

1: True

[1]

PKEY_FLT: Last turn-off is due to PONKEYn long key press hard-fault source while

PKEY_FLT_CNT > PKEY_FLT_CNT_MAX.

0: False

1: True

[0]

SWOFF: Last turn-off is due to software switch OFF

(SWOFF bit set and RREQ_EN bit clear in the MAIN_CR register).

0: False

1: True

STPMIC25

DS14278 - Rev 3

page 68/145

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