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STPMIC25 Datasheet(PDF) 60 Page - STMicroelectronics |
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STPMIC25 Datasheet(HTML) 60 Page - STMicroelectronics |
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60 / 145 page  6 Register descriptions 6.1 Register map All NVM_xxx bits of shadow registers have related xxx mirror bits in the control registers section allowing the software to override the NVM’s predefined values at runtime. Each time the NVM is reloaded, related xxx mirror bits are also reloaded with the NVM’s predefined values. All bits "reserved" in registers with R/W must not be modified. So, before writing on a register having a "reserved" bit, the user should read the content of the register and should only modify bits that are not "reserved," then write to the register. Hex Register Name R/W BITS[7:0] 7 6 5 4 3 2 1 0 Status registers 0x00 PRODUCT_ID R PMIC_REF_ID[3:0] PMIC_NVM_ID[3:0] 0x01 VERSION_SR R MAJOR_VERSION[3:0] MINOR_VERSION[3:0] 0x02 TURN_ON_SR R - - - - AUTO VBUS WKUP PKEY 0x03 TURN_OFF_SR R - - WDG_FLT THSDN_F LT OCP_FLT VIN_FLT PKEY_FLT SWOFF 0x04 RESTART_SR R - R_RST R_WDG_F LT R_THSDN _FLT R_OCP_F LT R_VIN_FL T R_PKEY_ FLT R_SWOFF 0x05 OCP_SR1 R OCP_REF DDR OCP_BUC K7 OCP_BUC K6 OCP_BUC K5 OCP_BUC K4 OCP_BUC K3 OCP_BUC K2 OCP_BUC K1 0x06 OCP_SR2 R OCP_LDO 8 OCP_LDO 7 OCP_LDO 6 OCP_LDO 5 OCP_LDO 4 OCP_LDO 3 OCP_LDO 2 OCP_LDO 1 0x07 EN_SR1 R EN_REFD DR EN_BUCK 7 EN_BUCK 6 EN_BUCK 5 EN_BUCK 4 EN_BUCK 3 EN_BUCK 2 EN_BUCK 1 0x08 EN_SR2 R EN_LDO8 EN_LDO7 EN_LDO6 EN_LDO5 EN_LDO4 EN_LDO3 EN_LDO2 EN_LDO1 0x09 FS_CNT_SR1 R VIN_FLT_CNT[3:0] PKEY_FLT_CNT[3:0] 0x0A FS_CNT_SR2 R THSDN_FLT_CNT[3:0] OCP_FLT_CNT[3:0] 0x0B FS_CNT_SR3 R - - - - WDG_FLT_CNT[3:0] 0x0C MODE_SR R - - - OP_MODE LDO4_VIN _SRC PWRCTRL 3 PWRCTRL 2 PWRCTRL 1 Control registers 0x10 MAIN_CR R/W - STANDBY_PWRCTRL[ 1:0] PWRCTRL_POL[2:0] RREQ_EN SWOFF 0x11 VINLOW_CR R/W - VINLOW_HYST[1:0] VINLOW_RISE[2:0] VINLOW_ EN 0x12 PKEY_LKP_CR R/W PKEY_LKP_CONFIG[1: 0] - - PKEY_LKP_TMR[3:0] 0x13 WDG_CR R/W - - - - WDG_PWRCTRL[1:0] WDG_RST WDG_EN 0x14 WDG_TMR_CR R/W WDG_TMR_SET[7:0] 0x15 WDG_TMR_SR R WDG_TMR_CNT[7:0] 0x16 FS_OCP_CR1 R/W FS_OCP_ REFDDR FS_OCP_ BUCK7 FS_OCP_ BUCK 6 FS_OCP_ BUCK5 FS_OCP_ BUCK4 FS_OCP_ BUCK3 FS_OCP_ BUCK2 FS_OCP_ BUCK1 0x17 FS_OCP_CR2 R/W FS_OCP_ LDO8 FS_OCP_ LDO7 FS_OCP_ LDO6 FS_OCP_ LDO5 FS_OCP_ LDO4 FS_OCP_ LDO3 FS_OCP_ LDO2 FS_OCP_ LDO1 0x18 PADS_PULL_CR R/W PWRCTRL3_PULL[1:0] PWRCTRL2_PULL[1:0] PWRCTRL1_PULL[1:0] WKUP_PU PKEY_PU 0x19 BUCKS_PD_CR1 R/W BUCK4_PD[1:0] BUCK3_PD[1:0] BUCK2_PD[1:0] BUCK1_PD[1:0] STPMIC25 Register descriptions DS14278 - Rev 3 page 60/145 |
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