STPMIC25BPQR datasheet(51/145 Pages) STMICROELECTRONICS

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5.4.6.1

PWRCTRL delay high and delay low behaviors

PWRCTRL delay blocks are independent for each regulator. A delay block allows a PWRCTRLx signal to shift by

preprogrammed delays. Each delay block is composed of two parts (a delay high and a delay low). The first

operates at a high input level, and the second operates at a low input level.

Delay blocks are typically used to emulate power sequences between regulators when entering or leaving a low

power mode.

High level delay behavior:

When the input signal goes from low to high level, the “high level delay timer” (PWRCTRL_DLY_H[1:0]) is started.

Once the timer expires, the output goes high.

If the input signal changes from high to low before the “high level delay timer” expires, the “high level delay timer”

is stopped and reset, and the output keeps the previous value.

Low level delay behavior:

Same behavior as for the high level delay but on low level input.

When the input signal goes from high to low level, the “low level delay timer” (PWRCTRL_DLY_L[1:0]) is started.

Once the timer expires, the output goes low.

If the input signal changes from low to high before the “low level delay timer” expires, the “low level delay timer” is

stopped and reset, and the output keeps the previous value.

Note:

The "high level delay timer" and "low level delay timer" are both driven from a level (and not from an edge) to

ensure that the output is always copying the input after any delay expires.

Figure 16 illustrates this example, using the PWRCTRL2 to control the BUCK1 and the BUCK2:

Settings for the Figure 16 example:

PWRCTRL2_POL = 0; // PWRCTRL2 active low = bypass

// BUCK1 settings

BUCK1_PWRCTRL_CR[PWRCTRL_SEL[1:0]] = 2; // PWRCTRL2 as BUCK1 control source

BUCK1_PWRCTRL_CR[PWRCTRL_DLY_H[1:0]] = 0; // no delay on PWRCTRL2 going from low to high for

BUCK1

BUCK1_PWRCTRL_CR[PWRCTRL_DLY_L[1:0]] = 2; // 3 ms delay on PWRCTRL2 going from high to low for

BUCK1

BUCK1_PWRCTRL_CR[PWRCTRL_EN] = 1; // enable the PWRCTRL input feature for BUCK1

// BUCK2 settings

BUCK2_PWRCTRL_CR[PWRCTRL_SEL[1:0]] = 2; // PWRCTRL2 as BUCK2 control source

BUCK2_PWRCTRL_CR[PWRCTRL_DLY_H[1:0]] = 2; // 3 ms delay on PWRCTRL2 going from low to high for

BUCK2

BUCK2_PWRCTRL_CR[PWRCTRL_DLY_L[1:0]] = 0; // no delay on PWRCTRL2 going from high to low for

BUCK2

BUCK2_PWRCTRL_CR[PWRCTRL_EN] = 1; // enable the PWRCTRL input feature for BUCK2

Figure 16. Delay rising and delay falling behaviors example

Christophe Belet

christophe belet ST Microelectronics

Standard use case behavior

BUCK1_MAIN_CR

PWRCTRL2

BUCK1_ALT_CR

BUCK1_MAIN_CR

DELAYout

(BUCK1)

BUCK1

3 ms

DELAYout

(BUCK2)

3 ms

BUCK2_MAIN_CR

BUCK2_ALT_CR

BUCK2_MAIN_CR

BUCK2

<3 ms

3 ms

BUCK1_ALT_

BUCK1_MAIN_CR

3 ms

>3 ms

<3 ms

3 ms

BUCK1_ALT_CR

BUCK2_MAI

N_CR

BUCK2_ALT_CR

Corner use cases behavior

DELAYin

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 51/145

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