STPMIC25BPQR datasheet(40/145 Pages) STMICROELECTRONICS

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5.1.2.6

POWER_ON

When the PMIC transitions from POWER_UP to POWER_ON, it always goes into the RUN state first.

In the RUN state, the PMIC can be set to deliver power at full performance and features. Each regulator can

switch power states (MAIN_CR or ALT_CR) depending on the PWRCTRLx pin settings (see Section 5.4.6).

In the STANDBY application conditions state, the PMIC can reach the minimum of quiescent current by disabling

internal IPs and by reducing their performances, such as reference accuracy. The PMIC can be set in the

STANDBY state only if all buck converters are set in LP mode or turned OFF. See Table 6. Consumption in typical

application scenarios.

Note:

The PMIC exits from the STANDBY state in the case that any buck converter is set in HP mode.

When a turn-off condition or RSTn assertion from MPU occurs, the PMIC moves to the POWER_DOWN state.

In case of a hard-fault turn-off condition, before the PMIC leaves the POWER_ON state:

•

The corresponding hard-fault counter is incremented (see Table 24): xxx_FLT_CNT ++

•

The FLT_TMR is loaded with the corresponding hard-fault duration and started (see Table 24)

5.1.2.7

POWER_DOWN

The PMIC asserts RSTn, then sequentially turns-off the regulators starting with the regulators not enabled in the

power-up sequence (= rank0: enabled by software at runtime), then in reverse sequence order in the

POWER_UP state (see Section 5.2).

When the POWER_DOWN sequence ends, before the transition to the next state, the watchdog is disabled

(WDG_EN = 0) and status registers are updated according to the turn-off condition source:

•

TURN_ON_SR and TURN_OFF_SR and RESTART_SR and OCP_SR1 and OCP_SR2 are reset (cleared)

•

If RSTn is asserted by AP (PMIC transition to K in Table 26):

–

RESTART_SR[R_RST] bit is set

•

Else If SWOFF && RREQ_EN (PMIC transition to K in Table 26):

–

RESTART_SR[R_SWOFF] bit is set

•

Else If SWOFF && !RREQ_EN (PMIC transition to L in Table 26):

–

TURN_OFF_SR[SWOFF] is set

•

Else (it is a hard-fault turn-off condition, then depending on the hard-fault source):

–

If hard-fault is OCP:

◦

OCP_SR1 or OCP_SR2 is updated with the OCP fault source

–

If PMIC transitions to M:

◦

TURN_OFF_SR is updated with fault source

–

If PMIC transitions to K:

◦

RESTART_SR is updated with fault source

Note: If another turn-off condition is triggered during the POWER DOWN sequence, it is ignored. So, only the

original power-down trigger source is registered.

5.1.2.8

FAIL_SAFE_LOCK

The FAIL_SAFE_LOCK state is entered from the POWER_DOWN state with M transition (a hard-fault counter

xxx_FLT_CNT that exceeds the max number of PMIC restart occurrences xxx_FLT_CNT_MAX).

In the FAIL_SAFE_LOCK state, the PMIC is in the lowest power consumption state: all regulators are turned OFF,

voltage references are OFF, and RSTn is asserted by the PMIC.

The PMIC is locked in that state until it POR: a turn-on condition does not power-up the PMIC.

Nevertheless, the PMIC is allowed to skip the FAIL_SAFE_LOCK state in specific conditions of N transition (see

Section 5.4.5.2).

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 40/145

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