STPMIC25BPQR datasheet(41/145 Pages) STMICROELECTRONICS

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5.2

POWER_UP / POWER_DOWN sequence

The PMIC starts and stops regulators following sequential rank procedures called POWER_UP and

POWER_DOWN, respectively.

During POWER_UP each regulator is started at one of the 6-rank phases programmed in the NVM. Each rank

phase is separated by a delay (1.5 ms, 3 ms, 4.5 ms, and 6 ms) programmed in the NVM.

An additional delay can be programmed in the NVM to release the RSTn signal later than last rank phase. This

delay is also applied after the Turn_OFF condition, in between RSTn signal assertion and when the first regulator

is powered off (RANK0).

The default rank sequence for each regulator, default output voltage of each regulator, default rank duration, and

additional RSTn default delays are predefined in the NVM. Those values can be adapted by reprogramming the

PMIC NVM with expected values.

Figure 11. PMIC POWER_UP and POWER_DOWN sequence example

For RANK_DLY and RST_DLY, see Table 91

Note:

RANK0 means that the regulator is not turned ON.

5.2.1

OFF and CHECK&LOAD:

The PMIC is initially in the OFF state. The RSTn pin is asserted by the PMIC. Once a Turn_ON condition occurs,

the PMIC goes into the CHECK&LOAD state. As the turn-ON condition is valid (for example: VIN > VINOK) the

PMIC goes into the POWER_UP state.

5.2.2

POWER_UP:

In the POWER_UP state, RSTn is kept asserted by the PMIC.

The PMIC enables regulators sequentially by 1.5 ms slots (according to the default rank sequence and default

output voltage defined in the NVM).

For example (see Figure 11:

RANK1 (LDO1) then RANK2 (BUCK4) then RANK3 (BUCK2) then RANK4 (BUCK1) then RANK5 (LDO4).

Once the RANK5 ends, the PMIC releases RSTn and then it goes into the POWER_ON state.

Note:

Regulator RANK0 (BUCK6 in this example) is not turned ON automatically.

5.2.3

POWER_ON:

In the POWER_ON state, all regulators are managed by the application processor’s software (I²C control) or by

the PWRCTRL pin (see Section 5.3.5). In the example of Figure 11 BUCK6 is enabled by the AP’s software at

runtime.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 41/145

STPMIC25BPQR Datasheet(PDF) 41 Page - STMicroelectronics