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STPMIC25BPQR Datasheet(PDF) 90 Page - STMicroelectronics |
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STPMIC25BPQR Datasheet(HTML) 90 Page - STMicroelectronics |
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90 / 145 page ![]() 6.3.15 Mask reset buck control register (BUCKS_MRST_CR) Table 54. LDOS_MRST_CR 7 6 5 4 3 2 1 0 LDO8_MRST LDO7_MRST LDO6_MRST LDO5_MRST LDO4_MRST LDO3_MRST LDO2_MRST LDO1_MRST R/W R/W R/W R/W R/W R/W R/W R/W • Address: 0x1E • Default: 0x00 • Description: mask reset LDO control register. See Section 5.4.7.1. This register is initialized to the default value in the CHECK&LOAD state. [7] LDO8_MRST: mask reset setting 0: inactive 1: active [6] LDO7_MRST: mask reset setting 0: inactive 1: active [5] LDO6_MRST: mask reset setting 0: inactive 1: active [4] LDO5_MRST: mask reset setting 0: inactive 1: active [3] LDO4_MRST: mask reset setting 0: inactive 1: active [2] LDO3_MRST: mask reset setting 0: inactive 1: active [1] LDO2_MRST: mask reset setting 0: inactive 1: active [0] LDO1_MRST: mask reset setting 0: inactive 1: active STPMIC25 Register descriptions DS14278 - Rev 3 page 90/145 |
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