STPMIC25BPQR datasheet(21/145 Pages) STMICROELECTRONICS

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Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

VOUT-LO

Load transient

regulation(4)

LP mode, 0 < IOUT < 50 mA, ΔIOUT = 50 mA, tR = tF = 500 ns

VOUT-LI

Line transient

regulation

ΔVBUCKIN = 600 mV, IOUT = 500 mA, tR = tF = 10 μs, HP mode

VOUT-OVR

Power-up overshoot

2.8 V < VBUCKIN < 5.5 V, IOUT = 1 mA, TA = 25 °C

tLP-HP-BCK

Recovery time from LP

to HP mode

VOUT_LP = VOUT_HP

60 (4)

µs

tSU_BCK

Startup delay (delay

before voltage starts to

rise)

Delay time from PWRCTRL signal

(PWRCTRL_DLY = 0)

25 (3)

40 (4)

tSS_BCK

Soft-start duration

2.8 V < VBUCKIN < 5.5 V, 1 mA < IOUT < 100 mA, VOUT- = 1.5 V

235

400

SRBCK

Output voltage slew

rate

Slew rate during startup

3.7

6.3

mV/µs

DVS slew rate of a voltage programmed change low to high or high to

low, from VOUT = 0.5 V to 1.5 V

3.1

tSD_BCK

Shutdown duration

From VOUT = 1.5 V to VOUT < 0.2 V, 2.8 V < VBUCKIN < 5.5 V,

IOUT< 1 mA, slow PD

1.5

From VOUT=1.5 V to VOUT <0.2 V, 2.8 V < VBUCKIN < 5.5 V,

IOUT < 1 mA, fast PD

0.3

1. Guaranteed by design - not tested in production. Load transient performances are strongly impacted by the external passive component

characteristics. The load transient is also influenced by the parasitic elements of the PCB layout. For more info see the forthcoming AN.

2. The output ripple voltage is the result of the inductor ripple current flowing through the output capacitor and depends on the capacitance

value, ESR, and ESL. The actual output ripple voltage is also influenced by the parasitic elements of the PCB layout.

3. See 1: startup sequence.

4. Guaranteed by design - not tested in production.

3.4.11

BUCK4, BUCK5

Table 16. Electrical and timing parameter specifications (BUCK4, BUCK5)

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

BUCK4, BUCK5

VBUCKIN

Main input voltage

range

2.8

5.5

VOUT

Output voltage

VBUCKIN > Vout + 0.8 V, VBUCKIN > 2.8 V

Programmable value

1.5 to

4.2

Voltage programming step

100

VOUT-ACC

Output voltage open

loop accuracy

HP mode

1.5 V < VOUT < 3.3 V

-1.5

+1.5

LP mode

-4

VOUT-REG

Output load

regulation (1)

HP mode, CCM mode

1 mA < IOUT < 0.5 A

-1

VOUT-RIPP

Output voltage ripple

(2)

HP mode, 3.0 V < VBUCKIN < 5.5 V, 1.5 V < VOUT < 3.3 V

5 mA < IOUT < 500 mA

mVPP

HP mode, IOUT = 500 mA

Forced PWM mode ON, HP mode, IOUT = 250 mA

LP mode, IOUT = 50 mA

STPMIC25

Electrical and timing characteristics

DS14278 - Rev 3

page 21/145

STPMIC25BPQR Datasheet(PDF) 21 Page - STMicroelectronics

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