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STPMIC25BPQR Datasheet(PDF) 80 Page - STMicroelectronics

Part # STPMIC25BPQR
Description  Highly integrated power management IC for microprocessor units
PDF  145 Pages
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

STPMIC25BPQR Datasheet(HTML) 80 Page - STMicroelectronics

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6.3.4
Watchdog control register (WDG_CR)
Table 45. WDG_CR
7
6
5
4
3
2
1
0
reserved
reserved
reserved
reserved
WDG_PWRCTRL_SEL[1:0]
WDG_RST
WDG_EN
R
R
R
R
R/W
R/W
W/R0/SC
R/W
•
Address: 0x13
•
Default: 0b0000000X where X depends on the value programmed in the NVM
•
Description: Watchdog control register (see Section 5.4.10 ). This register is initialized to the default value
in the CHECK&LOAD state.
[7:4]
Reserved
[3:2]
WDG_PWRCTRL_SEL[1:0]: Watchdog suspends source selection.
00: No source (if WDG_EN = 1, watchdog timer always runs)
01: PWRCTRL1 WDG suspends control source
10: PWRCTRL2 WDG suspends control source
11: PWRCTRL3 WDG suspends control source
When the watchdog is enabled (WDG_EN = 1): if the PWRCTRLx control source is inactive, the
watchdog timer runs; if the PWRCTRLx control source is active, the watchdog timer is suspended
[1]
WDG_RST: watchdog timer reset
0: NA
1: Watchdog downcounter WDG_TMR_CNT[7:0] is reloaded with the value in
WDG_TMR_SET[7:0] (self-cleared bit)
[0]
WDG_EN: watchdog enable bit
0: watchdog is disabled
1: watchdog is enabled
Default value is defined by the NVM_WDG_EN NVM bit
STPMIC25
Register descriptions
DS14278 - Rev 3
page 80/145



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