STPMIC25BPQR datasheet(39/145 Pages) STMICROELECTRONICS

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Transition

symbol

State transition

Transition condition

POWER_DOWN to

FAIL_SAFE_LOCK

VIN_FLT_CNT > VIN_FLT_CNT_MAX ||

PKEY_FLT_CNT > PKEY_FLT_CNT_MAX ||

TSHDN_FLT_CNT > TSHDN_FLT_CNT_MAX ||

OCP_FLT_CNT > OCP_FLT_CNT_MAX ||

WDG_FLT_CNT > WDG_FLT_CNT_MAX

FAIL_SAFE_LOCK to OFF

Transition to force leaving the fail-safe locked state:

FAIL_SAFE_LOCK_DIS (NVM bit) ||

PKEY_LKP_FSLS (PONKEY Long Key Press Fail-Safe-Lock-Skip bit)

5.1.2

State explanations

5.1.2.1

NO_SUPPLY

VIN is below VINPOR_Fall - see Section 5.4.1. No output state can be guaranteed in this state.

5.1.2.2

INIT&LOAD

The INIT&LOAD state is immediately reached when VIN is higher than VINPOR_Rise.

STPMIC25 releases internal POR circuitry, it initializes, all registers are reset, the NVM load is performed (see

Section 5.5.2), and RSTn is asserted.

If the Auto_turn_on condition is true, PMIC makes a transition to the CHECK&LOAD state. Prior to leaving the

INIT&LOAD state, the TURN_ON_SR is reset, and then the TURN_ON_SR[AUTO] bit is set.

If the Auto_turn_on condition is false, STPMIC25 evaluates the PONKEYn and VBUS status. If the turn on

condition is not recognized, STPMIC25 makes the transition to the OFF state, otherwise it sets the proper bit in

TURN_ON_SR and makes the transition to the CHECK&LOAD state (see Table 21.).

5.1.2.3

OFF

The OFF state is entered from the INIT&LOAD state, the POWER_DOWN state, or the FAIL_SAFE_LOCK state.

In the OFF state, the PMIC is in the lowest power consumption state, and all regulators are turned OFF. The

voltage references are OFF and RSTn is asserted by PMIC.

All fail-safe counters are reset (xxx_FLT_CNT). Fail-safe timers (FLT_TMR), reset-fault-counter-timers

(RST_FLT_CNT_TMR), and watchdog timers are stopped.

The transition to the CHECK&LOAD state (see Table 21) is triggered by a turn-on condition (see Section 5.4.3)

Prior to leaving the OFF state, the TURN_ON_SR is reset, then the related turn-on condition bit is set in the

TURN_ON_SR register.

5.1.2.4

CHECK&LOAD

CHECK&LOAD is a transitional state from a user point of view. It prepares the PMIC to power-up.

The PMIC enables internal reference voltages, thermal monitoring, and VIN monitoring.

The NVM is reloaded into shadow registers. Some registers are initialized with default values from the NVM

content.

RSTn is asserted by the PMIC.

After the CHECK&LOAD state, the PMIC always transitions to the POWER-UP state if power-up conditions are

fulfilled (see Table 21 ) and the fault timer (FLT_TMR) ends. The fault timer waits before restarting the PMIC after

a hard-fault (see Section 5.4.5)

5.1.2.5

POWER_UP

The PMIC starts sequential regulators following a sequence that is predefined in the NVM and a default voltage

that is predefined in the NVM (see Section 5.2).

During the power-up sequence, RSTn is asserted by the PMIC. When the power-up sequence ends without a

hard-fault, the PMIC releases an RSTn signal.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 39/145

STPMIC25BPQR Datasheet(PDF) 39 Page - STMicroelectronics

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