STPMIC25BPQR datasheet(99/145 Pages) STMICROELECTRONICS

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6.5.11

LDO3 MAIN mode control register (LDO3_MAIN_CR)

Table 64. LDO3_MAIN_CR

SNK_SRC

BYPASS

VOUT[4:0]

R/W

•

Address: 0x52

•

Default: 0bXXXXXXXX where X depends on the value programmed in the NVM

•

Description: LDO3 MAIN mode control register.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control enable, bypass mode or SNK_SRC mode, and set the voltage of LDO3, which is applied to the MAIN

mode (see Section 5.4.6.

[7]

SNK_SRC: select sink/source mode operation (see Section 4.2.3 )

0: LDO3 operates in normal or bypass mode

1: LDO3 operates in sink/source mode

The default value is defined by the SNK_SRC bit of the NVM_LDO3_SHR NVM shadow register

Note: the SNK_SRC bit has higher priority than the BYPASS mode operation (in the case that both bits are set at the

same time)

[6]

BYPASS: select bypass mode operation

0: LDO3 operates in normal mode

1: LDO3 operates in bypass mode

The default value is defined by the BYPASS bit of the NVM_LDO3_SHR NVM shadow register

[5:1]

VOUT[4:0]: LDO3 output voltage settings. See Section 4.2.6

The default value is defined in the VOUT[4:0] bit field of the NVM_LDO3_SHR NVM shadow registers

[0]

EN:

0: LDO3 is disabled

1: LDO3 is enabled

The default value is defined in the LDO3_RANK[2:0] bit field of the NVM_LDOs_RANK_SHR2 NVM shadow registers. If

LDO3_RANK[2:0] = 0, LDO3 is disabled at power up; if LDO3_RANK[2:0] = y (with 6 > y > 0) LDO3 is enabled at power

up at rank y (see Section 5.2)

STPMIC25

DS14278 - Rev 3

page 99/145

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