STPMIC25BPQR datasheet(22/145 Pages) STMICROELECTRONICS

22 / 145 page

Symbol

Parameter

Test conditions

Min.

Typ.

Max.

Unit

IOUT_LP_PEAK

Peak output current

in LP mode

2.8 V < VBUCKIN < 5.5 V, tPEAK up to 1 ms

200

IBCKLIM

Inductor peak current

limit (with typical BoM

list)

Programmable value in NVM_BUCKS_IOUT_SHR

Ref. Table 1. Default configuration table NVM setting A and B version

Max output current steps (0.25 A, 0.5 A) can be defined based on the

selected inductor peak current limit level

1.1

1.5

fREFCLK

Reference switching

frequency

CCM mode

MHz

IQ_BCK

Total quiescent

current

IOUT = 0 mA, HP mode

130

300

µA

IOUT = 0 mA, LP mode

IBUCKIN_LKG Input leakage current BUCK output disabled, Tj = 25 °C

0.01

1.5

EFFBCK

Efficiency

VBUCKIN = 5 V, VOUT = 1.8 V

HP mode, Tj = 50 °C, LP mode, IOUT = 0.1 mA

LP mode, IOUT = 1 mA IOUT = 10 mA

IOUT = 100 mA

IOUT = 500 mA

VOUT-LO

Load transient

regulation (1)

HP mode; 3.0 V < VBUCKIN < 5.5 V,

ΔV (in-out) > 1.5 V,

5 mA < IOUT < 500 mA, ΔIOUT = 100 mA,

tR = tF = 1 µs, forced PWM mode ON

HP mode, 3.0 V < VBUCKIN < 5.5 V

ΔV (in-out) > 1.5 V,

5 mA < IOUT < 500 mA, ΔIOUT = 100 mA

tR = tF = 1µs, forced PWM mode OFF

LP mode, 0 < IOUT <5 0 mA, ΔIOUT = 50 mA, tR = tF = 1 µs

VOUT-LI

Line transient

regulation

ΔVBUCKIN = 600 mV, ΔIOUT = 0, tR = tF =10 μs

ΔV (in-out) > 1.5 V, 1.8 V < VOUT < 3.3 V, HP mode

1.5

VOUT-OVR

Power-up overshoot

2.8 V < VBUCKIN < 5.5 V, IOUT = 1 mA, TA = 25 °C, 1.5 V < VOUT < 4.2 V

tLP-HP-BCK

Recovery time from

LP to HP mode

VOUT_LP = VOUT_HP

40(3)

µs

tSU_BCK

Startup delay (delay

before voltage starts

to rise)

Delay time from PWRCTRL signal (PWRCTRL_DLY = 0)

25 (4)

40 (3)

µs

tSS_BCK

Soft-start duration

2.8 V < VBUCKIN < 5.5 V, 1 mA < IOUT < 100 mA, VOUT = 4.2 V

235

400

µs

SRBCK

Output voltage slew

rate

Slew rate during startup

10.3

17.5

mV/µs

DVS slew rate of a voltage programmed change low to high or high to

low, from VOUT = 1.5 V to 4.2 V

3.1

tSD_BCK

Shutdown duration

From VOUT = 3.3 V to VOUT < 0.2 V,

2.8 V < VBUCKIN < 5.5 V, IOUT < 1 mA, slow PD

1.5

From VOUT = 3.3 V to VOUT < 0.2 V,

2.8 V < VBUCKIN < 5.5 V, IOUT < 1 mA, fast PD

0.3

1. Guaranteed by design - not tested in production. Load transient performances are strongly impacted by the external passive components

characteristics. The load transient is also influenced by the parasitic elements of the PCB layout. For more info see the forthcoming AN.

2. See 1: startup sequence.

STPMIC25

Electrical and timing characteristics

DS14278 - Rev 3

page 22/145

STPMIC25BPQR Datasheet(PDF) 22 Page - STMicroelectronics

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