STPMIC25BPQR datasheet(53/145 Pages) STMICROELECTRONICS

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5.4.7

Reset management (RSTn) and mask_reset software option

RSTn is a bidirectional reset pin both for the PMIC and the application processor. It has a digital input/open drain

output topology with an internal pull-up resistor (RPU).

•

When the PMIC asserts RSTn, it drives the RSTn signal low (open drain internal transistor). The

application processor is forced into a reset state.

•

When the PMIC does not assert RSTn, the RSTn pin is in high impedance and the RSTn signal goes high

(due to the pull-up resistor) if the RSTn signal is not asserted low externally (for example: by a reset push-

button or from an application processor asserting the reset signal low). In that case, the PMIC RSTn pin

becomes a digital input and it monitors the RSTn signal.

In the POWER_ON state, the RSTn pin can be driven by the application processor or a reset push-button.

When the application processor asserts RSTn low more than the tRSTnAS duration, it immediately triggers a reset

sequence of the PMIC by performing a noninterruptible power cycle:

1. The PMIC asserts RSTn low (forcing the AP to keep it in reset, and in the case that the AP releases the reset

before the end of the sequence)

2. POWER_DOWN sequence

3. CHECK &LOAD

4. POWER_UP sequence

5. PMIC deasserts RSTn and monitors RSTn

6. PMIC waits for the RSTn signal to go high before entering POWER_ON (to prevent an infinite loop of reset

sequence)

The PMIC can detect a negative pulse on RSTn shorter than the tRSTnAS duration. The PMIC must detect a

negative pulse longer or equal to the tRSTnAS duration.

5.4.7.1

mask_reset software option

From step 2 to step 4 (in the above sequence), LDOs and buck regulators follow a POWER_DOWN sequence

followed by a POWER_UP sequence as defined in Section 5.2; except for regulators having the mask_reset

option bit set.

The mask_reset option can be defined for each regulator by setting the corresponding MRST bit in

corresponding BUCKS_MRST_CR or LDOS_MRST_CR registers.

For example, for BUCK4: set the BUCK4_MRST bit in BUCKS_MRST_CR.

When the mask_reset option is set to a regulator, the MAIN and ALTERNATE related registers are not reset and

content is maintained during and after the reset power cycle. Nevertheless, the PWRCTRLx settings are reset for

all regulators, including those having the mask_reset option set:

•

POWER_DOWN is not performed

•

MAIN and ALTERNATE register values are not reset and their contents are maintained with the current

value

•

PWRCTRLx register settings are reset (xxx_PWRCTRL_CR)

The PMIC always ends the power cycle in the POWER_ON state, regardless of the PWRCTRLx value, as all

PWRCTRLx settings have been reset during the power cycle.

If RSTn is asserted in MAIN mode, regulators having the mask_reset option set are not impacted at all by the

reset sequence, keeping VOUT, EN, and PREG_MODE unchanged.

In case RSTn is asserted in the ALTERNATE mode, VOUT, EN, and PREG_MODE switch to the content of the

[regulator]_MAIN_CR register values when the POWER_DOWN sequence ends before the POWER_UP

sequence starts.

The Figure 18 illustrates a reset power cycle of the PMIC.

STPMIC25

Feature descriptions

DS14278 - Rev 3

page 53/145

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