STPMIC25BPQR datasheet(92/145 Pages) STMICROELECTRONICS

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6.5

Power supply control registers

6.5.1

BUCKx MAIN mode control register 1 (BUCKx_MAIN_CR1) (x = 1 to 7)

reserved

VOUT[6:0]

R/W

•

Address: 0x20/0x25/0x2A/0x2F/0x34/0x39/0x3E

•

Default: 0b0XXXXXXX where X depends on the value programmed in the NVM

•

Description: BUCK1 to BUCK7 MAIN mode control register 1.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

set the voltage of BUCKx, which is applied to the MAIN mode (see Section 5.4.6 and 0 BUCKconverter).

[7]

reserved

[6:0]

VOUT[6:0]: Buck output voltage settings. See Table 25. BUCK output voltage settings.

The default value is defined in the BUCKx_VOUT[2:0] bit field of NVM_BUCKs_VOUT_SHRx NVM shadow registers.

6.5.2

BUCKx MAIN mode control register 2 (BUCKx_MAIN_CR2) (x = 1 to 7)

Table 55. BUCKx_MAIN_CR2

reserved

PREG_MODE[1:0]

R/W

•

Address: 0x21/0x26/0x2B/0x30/0x35/0x3A/0x3F

•

Default: 0b00000XXX where X depends on the value programmed in NVM

•

Description: BUCK1 to BUCK7 MAIN mode control register 2.

This register is initialized to the default value in the CHECK&LOAD state. The user can write to these registers to

control the enable and regulation modes of BUCKx, which are applied to the MAIN mode (see Section 5.4.6 and 0

BUCKconverter).

[7:3]

reserved

[2:1

PREG_MODE: select regulation mode

00: BUCKx operates in high power mode (HP)

01: BUCKx operates in low power mode (LP)

10: BUCKx operates in forced PWM mode (CCM)

11: reserved

[0]

EN:

0: BUCKx is disabled

1: BUCKx is enabled

The default value is defined in the BUCKx_RANK[2:0] bit field of NVM_BUCKs_RANK_SHR NVM shadow registers. If

BUCKx_RANK[2:0] = 0, BUCKx is disabled at power up; if BUCKx_RANK[2:0] = y (with 6 > y > 0) BUCKx is enabled at

power up at rank y (see Section 5.2)

STPMIC25

DS14278 - Rev 3

page 92/145

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