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STPMIC25BPQR Datasheet(PDF) 63 Page - STMicroelectronics |
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STPMIC25BPQR Datasheet(HTML) 63 Page - STMicroelectronics |
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63 / 145 page  Hex Register Name R/W BITS[7:0] 7 6 5 4 3 2 1 0 Status registers 0x62 LDO8_ALT_CR R/W - BYPASS VOUT[4:0] EN 0x63 LDO8_PWRCTRL_C R R/W PWRCTRL_DLY_H[1:0] PWRCTRL_DLY_L[1:0] PWRCTRL_SEL[1:0] PWRCTRL_CMD[1:0] 0x64 REFDDR_MAIN_CR R/W - - - - - - - EN 0x65 REFDDR_ALT_CR R/W - - - - - - - EN 0x66 REFDDR_PWRCTR L_CR R/W PWRCTRL_DLY_H[1:0] PWRCTRL_DLY_L[1:0] PWRCTRL_SEL[1:0] PWRCTRL_CMD[1:0] Interrupt control registers 0x70 INT_PENDING_R1 R VBUS_RI VBUS_FA VINLOW_ RI VINLOW_ FA WKP_RI WKP_FA PKEY_RI PKEY_FA 0x71 INT_PENDING_R2 R - - - - THW_RI THW_FA 0x72 INT_PENDING_R3 R REFDDR_ OC P BUCK7_O CP BUCK6_O CP BUCK5_O CP BUCK4_O CP BUCK3_O CP BUCK2_O CP BUCK1_O CP 0x73 INT_PENDING_R4 R LDO8_OC P LDO7_OC P LDO6_OC P LDO5_OC P LDO4_OC P LDO3_OC P LDO2_OC P LDO1_OC P 0x74 INT_CLEAR_R1 W/R0 VBUS_ CLR[1:0] VINLOW_ CLR[1:0] WKP_ CLR[1:0] PKEY_ CLR[1:0] 0x75 INT_CLEAR_R2 W/R0 - - - - - - THW _CLR 0x76 INT_CLEAR_R3 W/R0 REFDDR_ OCP_CLR BUCK7_O CP_CLR BUCK6_O CP_CLR BUCK5_O CP_CLR BUCK4_O CP_CLR BUCK3_O CP_CLR BUCK2_O CP_CLR BUCK1_O CP_CLR 0x77 INT_CLEAR_R4 W/R0 LDO8_OC P_CLR LDO7_OC P_CLR LDO6_OC P_CLR LDO5_OC P_CLR LDO4_OC P_CLR LDO3_OC P_CLR LDO2_OC P_CLR LDO1_OC P_CLR 0x78 INT_MASK_R1 R/W VBUS_ MASK[1:0] VINLOW_ MASK[1:0] WKP_MASK[1:0] PKEY_ MASK[1:0] 0x79 INT_MASK_R2 R/W - - - - - - THW_MASK[1:0] 0x7A INT_MASK_R3 R/W REFDDR_ OCP_MAS K BUCK7_O CP_MASK BUCK6_O CP_MASK BUCK5_O CP_MASK BUCK4_O CP_MASK BUCK3_O CP_MASK BUCK2_O CP_MASK BUCK1_O CP_MASK 0x7B INT_MASK_R4 R/W LDO8_OC P_MASK LDO7_OC P_MASK LDO6_OC P_MASK LDO5_OC P_MASK LDO4_OC P_MASK LDO3_OC P_MASK LDO2_OC P_MASK LDO1_OC P_MASK 0x7C INT_SRC_R1 R VBUS !VBUS VINLOW !VINLOW WKP !WKP PKEY !PKEY 0x7D INT_SRC_R2 R - - - - - - THW !THW 0x7E INT_SRC_R3 R REFDDR_ OC P_SRC BUCK7_O CP_SRC BUCK6_O CP_SRC BUCK5_O CP_SRC BUCK4_O CP_SRC BUCK3_O CP_SRC BUCK2_O CP_SRC BUCK1_O CP_SRC 0x7F INT_SRC_R4 R LDO1_OC P_SRC LDO1_OC P_SRC LDO1_OC P_SRC LDO1_OC P_SRC LDO1_OC P_SRC LDO1_OC P_SRC LDO1_OC P_SRC LDO1_OC P_SRC 0x80 INT_DBG_LATCH_R 1 W/R0 VBUS_FRC[1:0] VINLOW_FRC[1:0] WKP_FRC[1:0] PKEY_FRC[1:0] 0x81 INT_DBG_LATCH_R 2 W/R0 - - - - - - THW_FRC[1:0] 0x82 INT_DBG_LATCH_R 3 W/R0 REFDDR_ OC P_FRC BUCK1_O CP_FRC BUCK1_O CP_FRC BUCK1_O CP_FRC BUCK1_O CP_FRC BUCK1_O CP_FRC BUCK1_O CP_FRC BUCK1_O CP_FRC 0x83 INT_DBG_LATCH_R 4 W/R0 LDO1_OC P_FRC LDO1_OC P_FRC LDO1_OC P_FRC LDO1_OC P_FRC LDO1_OC P_FRC LDO1_OC P_FRC LDO1_OC P_FRC LDO1_OC P_FRC NVM user control registers 0x8E NVM_SR R - - - - - - WRITE_FA IL BUSY STPMIC25 Register descriptions DS14278 - Rev 3 page 63/145 |
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