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STPMIC25BPQR Datasheet(PDF) 74 Page - STMicroelectronics |
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STPMIC25BPQR Datasheet(HTML) 74 Page - STMicroelectronics |
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74 / 145 page  6.2.10 Fail-safe counter status register 1 (FS_CNT_SR1) Table 38. FS_CNT_SR1 7 6 5 4 3 2 1 0 VIN_FLT_CNT[3:0] PKEY_FLT_CNT[3:0] R R R R R R R R • Address: 0x09 • Default: 0x00 • Description: Fail-safe counters store the number of hard-fault occurrences. There is one fail-safe counter by hard fault source (see Section 5.4.5). FS_CNT_SR1 is reset in the OFF state. [7:4] VIN_FLT_CNT[3:0]: number of occurrences triggered by a VIN falling below VINOK_Fall hard-fault source. (This is valid only if VIN is kept higher than VINPOR_Fall; or PMIC fully resets) [3:0] PKEY_FLT_CNT[3:0]: number of occurrences triggered by a PONKEYn long key press hard-fault source. Note: When a counter (xxx_FLT_CNT[3:0]) reaches 0xF, all next counter increments keep the counter value at 0xF (and not restart to 0). 6.2.11 Fail-safe counter status register 2 (FS_CNT_SR2) Table 39. FS_CNT_SR2 7 6 5 4 3 2 1 0 TSHDN_FLT_CNT[3:0] OCP_FLT_CNT[3:0] R R R R R R R R • Address: 0x0A • Default: 0x00 • Description: Fail-safe counters store the number of hard-fault occurrences. There is one fail-safe counter by hard fault source (see Section 5.4.5). FS_CNT_SR2 is reset in the OFF state. [7:4] TSHDN_FLT_CNT[3:0]: number of occurrences triggered by a thermal shutdown hard-fault source. [3:0] OCP_FLT_CNT[3:0]: number of occurrences triggered by regulator overcurrent hard-fault source. Note: When a counter (xxx_FLT_CNT[3:0]) reaches 0xF, all next counter increments keep the counter value at 0xF (and not restart to 0). STPMIC25 Register descriptions DS14278 - Rev 3 page 74/145 |
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