AD9172 datasheet(39/146 Pages) AD

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Data Sheet

AD9172

JESD204B SERIAL DATA INTERFACE

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Rev. C | 39 of 146

Write each SRC_LANEy with the number (x) of the desired physical

lane (SERDINx±) from which to obtain data. By default, all logical

lanes use the corresponding physical lane as their data source. For

example, by default, SRC_LANE0 = 0; therefore, Logical Lane 0

obtains data from Physical Lane 0 (SERDIN0±). To use SERDIN4±

as the source for Logical Lane 0 instead, the user must write

SRC_LANE0 = 4.

Lane Inversion

be used to ease routing of the SERDINx± signals. For each Logical

Lane x, set Bit x of Register 0x334 to 1 to invert it.

Deframer

The AD9172 consists of two quad-byte deframers (QBDs) paged

by the LINK_PAGE control in Register 0x300, Bit 2. The deframer

accepts the 8-bit/10-bit encoded data from the deserializer (via the

crossbar switch), decodes it, and descrambles it into JESD204B

frames before passing it to the transport layer to be converted to

DAC samples. The deframer processes four symbols (or octets) per

processing clock (PCLK) cycle.

The deframer uses the JESD204B parameters that the user has

programmed into the register map to identify how the data is

packed, and unpacks it. The JESD204B parameters are described

in detail in the Transport Layer section; many of the parameters are

also needed in the transport layer to convert JESD204B frames into

samples.

Descrambler

The AD9172 provides an optional descrambler block using a self

synchronous descrambler with the following polynomial: 1 + x14 +

x15.

Enabling data scrambling reduces spectral peaks that are produced

when the same data octets repeat from frame to frame. It also

makes the spectrum data independent so that possible frequency

selective effects on the electrical interface do not cause data de-

pendent errors. Descrambling of the data is enabled by setting the

SCR bit (Register 0x453, Bit 7) to 1.

SYNCING LMFC SIGNALS

The AD9172 requires a synchronization (sync) to align the LMFC

and other internal clocks before the SERDES links are brought

online. The synchronization is a one-shot sync, where the synchro-

nization process begins on the next edge of the alignment signal

following the assertion of the SYSREF_MODE_ ONESHOT control

in Register 0x03A, Bit 1.

In Subclass 1, the SYSREF± rising edge acts as the alignment

edge; in Subclass 0, an internal processing clock acts as the

alignment edge. When a sync has completed, the SYNC_ROTA-

TION_DONE (Register 0x03A, Bit 4) bit is asserted and remains

asserted until another sync is requested.

After a synchronization occurs, the JESD204B link can be enabled.

In Subclass 1, the latency of the JESD204B system is deterministic

and allows synchronization across multiple devices, if desired.

SYSREF± Signal

The SYSREF± signal is a differential source synchronous input that

synchronizes the LMFC signals in both the transmitter and receiver

in a JESD204B Subclass 1 system to achieve deterministic latency.

The SYSREF± signal is a rising edge sensitive signal that is

sampled by the device clock rising edge. It is best practice that

the device clock and SYSREF± signals be generated by the

same source, such as the HMC7044 clock generator, so that the

phase alignment between the signals is fixed. When designing

for optimum deterministic latency operation, consider the timing

distribution skew of the SYSREF± signal in a multipoint link system

(multichip).

The AD9172 supports a periodic SYSREF± signal. The periodicity

can be continuous, strobed, or gapped periodic. The SYSREF±

signal can be dc-coupled with a common-mode voltage of 0.6

V to 2.2 V and differential swing of 200 mV p-p to 1 V p-p.

When dc-coupled, a small amount of common-mode current (up

to 0.3 mA) is drawn from the SYSREF± pins. See Figure 53 and

Figure 54 for the SYSREF± internal circuit for dc-coupled and ac-

coupled configurations. Ensure that the SYSREF_INPUTMODE bit

(Register 0x084, Bit 6) is set to 1, dc-coupled, to prevent overstress

on the SYSREF± receiver pins.

Figure 53. DC-Coupled SYSREF± Receiver Circuitry

Figure 54. AC-Coupled SYSREF± Receiver Circuitry

To avoid this common-mode current draw, the SYSREF± receiver

can be ac-coupled using a 50% duty cycle periodic SYSREF±

signal with ac coupling capacitors. If ac-coupled, the ac coupling

capacitors combine with the resistors shown in Figure 54 to make

a high-pass filter with an RC time constant of τ = RC. Select C

such that τ > 4/SYSREF± frequency. In addition, the edge rate must

be sufficiently fast to allow SYSREF± sampling clocks to correctly

sample the rising SYSREF± edge before the next sample clock.

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