AD9172 datasheet(65/146 Pages) AD

65 / 146 page

Data Sheet

AD9172

ANALOG INTERFACE CONSIDERATIONS

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Rev. C | 65 of 146

DAC INPUT CLOCK CONFIGURATIONS

The AD9172 DAC sample clock or device clock (DACCLK) can be

sourced directly through CLKIN± (Pin H12 and Pin J12) or by using

the on-chip, integrated, integer PLL VCO with the same CLKIN± dif-

ferential input serving as the reference. Clock multiplying employs

the on-chip DAC PLL that accepts a reference clock operating at a

submultiple of the desired DACCLK rate. The PLL then multiplies

the reference clock up to the desired DACCLK frequency, which

generates all the clocks within the AD9172, as shown in Figure 84.

The AD9172 contains a low jitter, differential clock receiver that is

capable of interfacing directly to a differential or single-ended clock

source. Because the input is self biased with a nominal impedance

of 100 Ω, it is recommended that the clock source be ac-coupled

to the CLKIN± input pins. Improved phase noise performance can

be achieved with a higher clock input level. The quality of the

clock source, as well as its interface to the AD9172 clock input,

directly impacts ac performance. Select the phase noise and spur

characteristics of the clock source to meet the target application

requirements.

Figure 82. Clock Receiver Input Simplified Equivalent Circuit

Figure 83. Phase Noise vs. Frequency Offset; Direct Clock and PLL Phase Noise, 12 GHz DAC Sample Rate, 1.65 GHz Output Frequency

AD9172 Datasheet(PDF) 65 Page - Analog Devices