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AD9172 Datasheet(PDF) 87 Page - Analog Devices |
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AD9172 Datasheet(HTML) 87 Page - Analog Devices |
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87 / 146 page  Data Sheet AD9172 REGISTER DETAILS analog.com Rev. C | 87 of 146 Table 60. Register Details Addr. Name Bits Bit Name Settings Description Reset Access 0x000 SPI_INTFCONFA 7 SOFTRESET_M Soft reset (mirror). Set this bit to mirror Bit 0. 0x0 R 6 LSBFIRST_M LSB first (mirror). Set this bit to mirror Bit 1. 0x0 R 5 ADDRINC_M Address increment (mirror). Set this bit to mirror Bit 2. 0x0 R 4 SDOACTIVE_M SDO active (mirror). Set this bit to mirror Bit 3. 0x0 R 3 SDOACTIVE SDO active. Enables 4-wire SPI bus mode. 0x0 R/W 2 ADDRINC Address increment. When set, this bit causes incrementing streaming addresses; otherwise, descending addresses are generated. 0x0 R/W 1 Streaming addresses are incremented. 0 Streaming addresses are decremented. 1 LSBFIRST LSB first. When set, this bit causes SPI input and output data to be oriented as LSB first. If this bit is clear, data is oriented as MSB first. 0x0 R/W 1 Shift LSB in first. 0 Shift MSB in first. 0 SOFTRESET Soft reset. This bit automatically clears to 0 after performing a reset operation. Setting this bit initiates a reset. This bit autoclears after the soft reset is complete. 0x0 R/W 1 Pulse the soft reset line. 0 Reset the soft reset line. 0x001 SPI_INTFCONFB 7 SINGLEINS Single instruction. 0x0 R/W 1 Perform single transfers. 0 Perform multiple transfers. 6 CSSTALL CS stalling. 0x0 R/W 0 Disable CS stalling. 1 Enable CS stalling. [5:0] RESERVED Reserved. 0x0 R/W 0x003 SPI_CHIPTYPE [7:0] CHIP_TYPE Chip type. 0x4 R 0x004 SPI_PRODIDL [7:0] PROD_ID[7:0] Product ID. 0x72 R 0x005 SPI_PRODIDH [7:0] PROD_ID[15:8] Product ID. 0x91 R 0x006 SPI_CHIPGRADE [7:4] PROD_GRADE Product grade. 0x0 R [3:0] DEV_REVISION Device revision. 0x2 R 0x008 SPI_PAGEINDX [7:6] MAINDAC_PAGE Sets the main DAC paging. Each high bit in this field pages a DAC starting at the LSB. Both main DACs can be paged and programmed at the same time if desired. 0x3 R/W [5:0] CHANNEL_PAGE Sets channel paging. Each high bit in this field pages a complex channel starting at the LSB. Multiple channels can be paged and programmed at a time if desired. 0x3F R/W 0x00A SPI_SCRATCHPAD [7:0] SCRATCHPAD Scratch pad read/write register. 0x0 R/W 0x010 CHIP_ID_L [7:0] CHIP_ID[7:0] Chip ID serial number. 0x0 R 0x011 CHIP_ID_M1 [7:0] CHIP_ID[15:8] Chip ID serial number. 0x0 R 0x012 CHIP_ID_M2 [7:0] CHIP_ID[23:16] Chip ID serial number. 0x0 R 0x013 CHIP_ID_H [7:0] CHIP_ID[31:24] Chip ID serial number. 0x0 R 0x020 IRQ_ENABLE [7:5] RESERVED Reserved. 0x0 R 4 EN_SYSREF_JITTER Enable SYSREF± jitter interrupt. 0x0 R/W 3 EN_DATA_READY Enable JESD204B receiver ready (JRX_DATA_READY) low interrupt. 0x0 R/W |
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