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AD9172 Datasheet(PDF) 30 Page - Analog Devices |
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AD9172 Datasheet(HTML) 30 Page - Analog Devices |
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30 / 146 page  Data Sheet AD9172 SERIAL PORT OPERATION analog.com Rev. C | 30 of 146 To prevent confusion and to ensure consistency between devices, the chip tests the first nibble following the address phase, ignoring the second nibble. This test is completed independently from the LSB first bits and ensures that there are extra clock cycles following the soft reset bits (Register 0x000, Bit 0 and Bit 7). This test of the first nibble only applies when writing to Register 0x000. Figure 40. Serial Register Interface Timing, MSB First, Register 0x000, Bit 6 and Bit 1 = 0 Figure 41. Serial Register Interface Timing, LSB First, Register 0x000, Bit 6 and Bit 1 = 1 Figure 42. Timing Diagram for Serial Port Register Read Figure 43. Timing Diagram for Serial Port Register Write |
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