AD9172 datasheet(29/146 Pages) AD

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Data Sheet

AD9172

SERIAL PORT OPERATION

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Rev. C | 29 of 146

The serial port is a flexible, synchronous serial communications port

that allows easy interfacing with many industry-standard microcon-

trollers and microprocessors. The serial input/output is compatible

with most synchronous transfer formats, including both the Motoro-

la, Inc., SPI and Intel® SSR protocols. The interface allows read

and write access to all registers that configure the AD9172. MSB

first or LSB first transfer formats are supported. The serial port in-

terface can be configured as a 4‑wire interface or a 3-wire interface

in which the input and output share a single pin input/output (SDIO).

Figure 39. Serial Port Interface Pins (144-Ball BGA_ED)

There are two phases to a communication cycle with the AD9172.

Phase 1 is the instruction cycle (the writing of an instruction byte

into the device), coincident with the first 16 SCLK rising edges. The

instruction word provides the serial port controller with information

regarding the data transfer cycle, Phase 2 of the communication

cycle. The Phase 1 instruction word defines whether the upcoming

data transfer is a read or write, along with the starting register

address for the following data transfer.

A logic high on the CS pin followed by a logic low resets the serial

port timing to the initial state of the instruction cycle. From this

state, the next 16 rising SCLK edges represent the instruction bits

of the current input/output operation.

The remaining SCLK edges are for Phase 2 of the communication

cycle. Phase 2 is the actual data transfer between the device

and the system controller. Phase 2 of the communication cycle

is a transfer of one or more data bytes. Eight × N SCLK cycles

are required to transfer N bytes during the transfer cycle. Reg-

isters change immediately upon writing to the last bit of each

transfer byte, except for the FTW and NCO phase offsets, which

change only when the frequency tuning word load request bit

(DDSM_FTW_LOAD_REQ or DDSC_FTW_LOAD_REQ) is set.

DATA FORMAT

The instruction byte contains the information shown in Table 14.

Table 14. Serial Port Instruction Word

I15 (MSB)

I[14:0]

R/W

A[14:0]

R/W, Bit 15 of the instruction word, determines whether a read or

a write data transfer occurs after the instruction word write. Logic 1

indicates a read operation, and Logic 0 indicates a write operation.

A14 to A0, Bit I14 to Bit I0 of the instruction word, determine

the register that is accessed during the data transfer portion of

the communication cycle. For multibyte transfers, A[14:0] is the

starting address. The remaining register addresses are generated

by the device based on the address increment bit. If the address

increment bits are set high (Register 0x000, Bit 5 and Bit 2),

multibyte SPI writes start on A[14:0] and increment by 1 every eight

bits sent/received. If the address increment bits are set to 0, the

address decrements by 1 every eight bits.

SERIAL PORT PIN DESCRIPTIONS

Serial Clock (SCLK)

The serial clock pin synchronizes data to and from the device and

runs the internal state machines. The maximum frequency of SCLK

is 80 MHz. All data input is registered on the rising edge of SCLK.

All data is driven out on the falling edge of SCLK.

Chip Select (CS)

An active low input starts and gates a communication cycle. CS

allows more than one device to be used on the same serial commu-

nications lines. The SDIO pin goes to a high impedance state when

this input is high. During the communication cycle, the chip select

must stay low.

Serial Data Input/Output (SDIO)

This pin is a bidirectional data line. In 4-wire mode, this pin acts as

the data input and SDO acts as the data output.

SERIAL PORT OPTIONS

The serial port can support both MSB first and LSB first data

formats. This functionality is controlled by the LSB first bit (Regis-

ter 0x000, Bit 6 and Bit 1). The default is MSB first (LSBFIRST bit =

0).

When the LSB first bits = 0 (MSB first), the instruction and data bits

must be written from MSB to LSB. R/W is followed by A[14:0] as the

instruction word, and D[7:0] is the data-word. When the LSB first

bits = 1 (LSB first), the opposite is true. A[0:14] is followed by R/W,

which is subsequently followed by D[0:7].

The serial port supports a 3-wire or 4-wire interface. When the SDO

active bits = 1 (Register 0x000, Bit 4 and Bit 3), a 4-wire interface

with a separate input pin (SDIO) and output pin (SDO) is used.

When the SDO active bits = 0, the SDO pin is unused and the SDIO

pin is used for both the input and the output.

Multibyte data transfers can be performed as well by holding the

CS pin low for multiple data transfer cycles (eight SCLKs) after the

first data transfer word following the instruction cycle. The first eight

SCLKs following the instruction cycle read from or write to the regis-

ter provided in the instruction cycle. For each additional eight SCLK

cycles, the address is either incremented or decremented and the

read/write occurs on the new register. The direction of the address

can be set using ADDRINC or ADDRINC_M (Register 0x000, Bit

5 and Bit 2). When ADDRINC or ADDRINC_M is 1, the multicycle

addresses are incremented. When ADDRINC or ADDRINC_M is 0,

the addresses are decremented. A new write cycle can always be

initiated by bringing CS high and then low again.

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