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AD9172 Datasheet(PDF) 73 Page - Analog Devices |
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AD9172 Datasheet(HTML) 73 Page - Analog Devices |
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73 / 146 page  Data Sheet AD9172 START-UP SEQUENCE analog.com Rev. C | 73 of 146 Table 56. JESD204B SERDES Required Interface Setup R/W Register Bits Value Description W 0x216 [7:0] 0x05 SERDES required register write. W 0x212 [7:0] 0xFF SERDES required register write. W 0x212 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x87 SERDES required register write. W 0x216 [7:0] 0x11 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x200 [7:0] 0x00 Power up the SERDES circuitry blocks. Pause Wait 100 ms. W 0x210 [7:0] 0x86 SERDES required register write. W 0x216 [7:0] 0x40 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x86 SERDES required register write. W 0x216 [7:0] 0x00 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x210 [7:0] 0x87 SERDES required register write. W 0x216 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x01 SERDES required register write. W 0x213 [7:0] 0x00 SERDES required register write. W 0x280 [7:0] 0x05 SERDES required register write. W 0x280 [7:0] 0x01 Start up SERDES PLL circuitry blocks and initiate SERDES PLL calibration. R 0x281 0 0b1 Ensure Bit 0 of this register reads back 1 to indicate the SERDSES PLL is locked. Crossbar mapping writes the SERDINx input pin that is the source for each given logical lane in these registers. A value of x corresponds to mapping data from the SERDINx± pin to the logical lane of the control bit field. These values in Table 57 vary with different PCB layout routing. Table 57. Transport Layer Setup, Synchronization, and Enable Links R/W Register Bits Value Description W 0x308 [7:0] Crossbar setup. Program the physical lane value that is providing data (the source) for each of the logical lanes. [5:3] = Logical Lane 1 source, [2:0] = Logical Lane 0 source. W 0x309 [7:0] [5:3] = Logical Lane 3 source, [2:0] = Logical Lane 2 source. W 0x30A [7:0] [5:3] = Logical Lane 5 source, [2:0] = Logical Lane 4 source. W 0x30B [7:0] [5:3] = Logical Lane 7 source, [2:0] = Logical Lane 6 source. W 0x306 [7:0] 0x0C If operating in Subclass 0, this register write is not needed. W 0x307 [7:0] 0x0C If operating in Subclass 0, this register write is not needed. W 0x304 [7:0] If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be determined by following one of the deterministic latency methods (with or without known delays), as mentioned in the Link Delay section. W 0x305 [7:0] If operating in Subclass 0, this register write is not needed. For Subclass 1, these values must be determined by following one of the deterministic latency methods (with or without known delays), as mentioned in the Link Delay section. W 0x03B [7:0] 0xF1 Enable the sync logic, and set the rotation mode to reset the synchronization logic upon a sync reset trigger. W 0x03A [7:0] 0x02 Set up sync for one-shot sync mode. SYSREF± If operating in Subclass 1, send SYSREF± pulse edges to the device for synchronization alignment. W 0x300 3 LINK_MODE Corresponds to the mode selection made in Register 0x110. 0b0 = single-link mode. |
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