AD9172 datasheet(94/146 Pages) AD

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Data Sheet

AD9172

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Rev. C | 94 of 146

Table 60. Register Details

Addr.

Name

Bits

Bit Name

Settings

Description

Reset

Access

The calculation for Code 0 to Code 9 is as follows:

ADC driver swing = 993 mV − CLKOUT_

SWING × 77 mV.

The calculation for Code 10 to Code 19 is as follows:

ADC driver swing = (20 − CLKOUT_SWING × 77 mV)

− 1 V.

0x08F

ADC_CLK_CTRL2

[7:1]

RESERVED

Reserved.

0x0

PD_CLKOUT_

Powers down the CLKOUT± output driver.

0x0

R/W

DRIVER

0x090

DAC_POWERDOWN

[7:2]

RESERVED

Reserved.

0x0

DAC_PD1

Powers down DAC1.

0x1

R/W

Power up DAC1.

Power down DAC1.

DAC_PD0

Powers down DAC0.

0x1

R/W

Power up DAC0.

Power down DAC0.

0x091

ACLK_CTRL

[7:1]

RESERVED

Reserved.

0x0

R/W

ACLK_

Analog clock receiver power-down.

0x1

R/W

POWERDOWN

0x094

PLL_CLK_DIV

[7:2]

RESERVED

Reserved.

0x0

PLL_VCO_DIV3_EN

Enable PLL output clock divide by 3.

0x0

R/W

PLL_VCO_DIV2_EN

Enable PLL output clock divide by 2.

0x0

R/W

DAC clock = PLL VCO clock frequency.

DAC clock = PLL VCO clock frequency ÷ 2.

0x095

PLL_BYPASS

[7:1]

RESERVED

Reserved.

0x0

PLL_BYPASS

Enable direct clocking (bypassing the PLL clock).

0x0

R/W

Use the internal PLL to generate the DAC clock.

Bypass the PLL and directly clock with the DAC clock

frequency.

0x09A

NVM_CTRL

PD_BGR

Bias power-down. Set this bit to 1 to power down the

internal bias.

0x0

R/W

[6:0]

RESERVED

Reserved.

0x0

R/W

0x0C0

DELAY_LINE_PD

[7:6]

RESERVED

Reserved.

0x0

DLL_CTRL0B

DLL control. Set this bit to 0 to power up the delay

line during the device configuration sequence.

0x1

R/W

DLL_CTRL0A

DLL control. Set this bit to 0 to power up the delay

line during the device configuration sequence.

0x1

R/W

[3:1]

RESERVED

Reserved.

0x0

DLL_PD

Power down delay line. Set this bit to 0 to power

up the delay line during the device configuration

sequence.

0x1

R/W

Power up and enable the delay line.

Power down and bypass the delay line.

0x0C1

DLL_CTRL0

[7:6]

DLL_CTRL1C

DAC control setting. Set this control to 1 for optimal

performance.

0x1

R/W

DLL_CTRL1B

DLL control search mode. If the DAC frequency is

<4.5 GHz, set this bit to 0; otherwise, set this bit to 1.

0x1

R/W

[4:3]

DLL_CTRL1A

DLL control search direction. Set this control to 1 for

optimal performance.

0x2

R/W

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