AD9172 datasheet(72/146 Pages) AD

72 / 146 page

Data Sheet

AD9172

START-UP SEQUENCE

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Rev. C | 72 of 146

Table 55. Main DAC Datapath Setup: PA Protect and Main NCOs

R/W

Bits

Value

Description

0x115

[7:0]

Write DDSM_FTW[15:8].

0x116

[7:0]

Write DDSM_FTW[23:16].

0x117

[7:0]

Write DDSM_FTW[31:24].

0x118

[7:0]

Write DDSM_FTW[39:32].

0x119

[7:0]

Write DDSM_FTW[47:40].

0x11C

[7:0]

Write DDSM_NCO_PHASE_OFFSET[7:0]. Calculation: DDSM_NCO_PHASE_OFFSET = (degrees offset/180) × 215.

0x11D

[7:0]

Write DDSM_NCO_PHASE_OFFSET[15:8].

If using NCO modulus mode, also program modulus parameters. If not, skip this section. For modulus NCO mode: (fCARRIER/fDAC)

= (X + (A/B))/248, where DDSM_ACC_DELTA = A, DDSM_ACC_MODULUS = B, and DDSM_FTW = X.

0x124

[7:0]

Write DDSM_ACC_MODULUS[7:0].

0x125

[7:0]

Write DDSM_ACC_MODULUS[15:8].

0x126

[7:0]

Write DDSM_ACC_MODULUS[23:16].

0x127

[7:0]

Write DDSM_ACC_MODULUS[31:24].

0x128

[7:0]

Write DDSM_ACC_MODULUS[39:32].

0x129

[7:0]

Write DDSM_ACC_MODULUS[47:40].

0x12A

[7:0]

Write DDSM_ACC_DELTA[7:0].

0x12B

[7:0]

Write DDSM_ACC_DELTA[15:8].

0x12C

[7:0]

Write DDSM_ACC_DELTA[23:16].

0x12D

[7:0]

Write DDSM_ACC_DELTA[31:24].

0x12E

[7:0]

Write DDSM_ACC_DELTA[39:32].

0x12F

[7:0]

Write DDSM_ACC_DELTA[47:40].

0x113

0b1

Update all NCO phase and FTW words.

Table 56. JESD204B SERDES Required Interface Setup

R/W

Bits

Value

Description

0x240

[7:0]

0xAA or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0xAA;

otherwise, set to 0xFF.

0x241

[7:0]

0xAA or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0xAA;

otherwise, set to 0xFF.

0x242

[7:0]

0x55 or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0x55; otherwise,

set to 0xFF.

0x243

[7:0]

0x55 or 0xFF EQ settings determined by amount of insertion loss according to Table 22. For insertion loss ≤ 11 dB, set to 0x55; otherwise,

set to 0xFF.

0x244

[7:0]

0x1F

EQ settings.

0x245

[7:0]

0x1F

EQ settings.

0x246

[7:0]

0x1F

EQ settings.

0x247

[7:0]

0x1F

EQ settings.

0x248

[7:0]

0x1F

EQ settings.

0x249

[7:0]

0x1F

EQ settings.

0x24A

[7:0]

0x1F

EQ settings.

0x24B

[7:0]

0x1F

EQ settings.

0x201

[7:0]

Power down unused PHYs. Bit x corresponds to SERDINx± pin power-down.

0x203

If in single-link mode, set to 0x01. If in dual-link mode and using both signals, set to 0x00.

0b0

Power up driver by setting this bit to 0.

Power up driver by setting this bit to 0 if using dual link and both signals.

0x253

[7:0]

0x01

Set to be LVDS output. For CMOS output on , set Bit 0 to 0.

0x254

[7:0]

0x01

Set to be LVDS output. For CMOS output on , set Bit 0 to 0.

0x210

[7:0]

0x16

SERDES required register write.

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