AD9172 datasheet(40/146 Pages) AD

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Data Sheet

AD9172

JESD204B SERIAL DATA INTERFACE

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Rev. C | 40 of 146

When ac coupling the SYSREF± inputs, ensure that the SYS-

REF_INPUTMODE bit (Register 0x084, Bit 6) is set to 0, ac‑cou-

pled, to enable the internal receiver biasing circuitry and prevent

overstress on the SYSREF± receiver pins. AC coupling allows a

differential voltage swing from 200 mV to 1 V on the SYSREF±

pins.

SYSREF± Sampling

The SYSREF± signal is sampled by a divide by 4 version of the

DAC clock. Therefore, the minimum pulse width of the SYSREF±

signal must exceed 4 DAC clock periods to ensure accurate sam-

pling. The delay between the SYSREF± and DAC clock input signal

does not need to be timing constrained.

By default, the first SYSREF± rising edge at the SYSREF± inputs

that is detected after asserting the SYSREF_MODE_ONESHOT bit

(Register 0x03A, Bit 1) begins the synchronization and aligns the

internal LMFC signal with the sampled SYSREF± edge.

SYSREF± edges are ignored after the SYSREF_MODE_ ONE-

SHOT bit is asserted before the synchronization takes place. For

example, if SYSREF_COUNT is set to 3, the AD9172 does not

sync after the SYSREF_MODE_ONESHOT bit is asserted until the

arrival of the 4th SYSREF± edge.

SYSREF± Jitter IRQ

In Subclass 1, after the one-shot synchronization occurs, the SYS-

REF± signal is monitored to ensure that the subsequent SYSREF±

edges do not deviate from the internal LMFC clock by more than a

target amount.

the error window allowed, in DAC clock units. If a SYSREF± edge

varies from the internal LMFC clock by more than the number

of DAC clock units set in SYSREF_ERR_WINDOW, the IRQ_SYS-

REF_JITTER is asserted.

Table 24. SYSREF± Jitter Window Tolerance

SYSREF± Jitter Window Tolerance

(DAC Clock Cycles)

SYSREF_ERR_WINDOW (Register

0x039, Bits[5:0])1

±½

0x00

±4

0x04

±8

0x08

±12

0x0C

±16

0x10

±20

0x14

+24

0x18

±28

0x1C

1 The two least significant digits are ignored because the SYSREF± signal

is sampled with a divide by 4 version of the DAC clock. As a result, the

jitter window is set by this divide by 4 clock rather than the DAC clock. It

Table 24. SYSREF± Jitter Window Tolerance

SYSREF± Jitter Window Tolerance

(DAC Clock Cycles)

SYSREF_ERR_WINDOW (Register

0x039, Bits[5:0])1

is recommended that at least a four-DAC clock SYSREF± jitter window be

chosen.

The IRQ_SYSREF_JITTER can be configured as described in

the Interrupt Request Operation section to indicate the SYSREF±

signal has varied, and to request the SPI sequence for a sync be

performed again.

Sync Procedure

The procedure for enabling the sync is as follows:

1. Set up the DAC and the SERDES PLL, and enable the CDR

(see the Start-Up Sequence section).

2. Set Register 0x03B to 0xF1 to enable the synchronization

circuitry. If using the soft on/off feature, set Register 0x03B to

0xF3 to ramp the datapath data before and after the synchroni-

zation.

3. If Subclass 1, configure the SYSREF± settings as follows:

a. Set Register 0x039 (SYSREF± jitter window). See Table 24

for settings.

b. Set Register 0x036 = SYSREF_COUNT; leave as 0 to

bypass.

4. Perform a one-shot sync.

a. Set Register 0x03A = 0x00. Clear one-shot mode if already

enabled.

b. Set Register 0x03A = 0x02. Enable one-shot sync mode.

5. If Subclass 1, send a SYSREF± edge. If pulse counting, multi-

ple SYSREF± edges are required. Sending SYSREF± edges

triggers the synchronization.

6. Read back the SYNC_ROTATION_DONE bit (Register 0x03A,

Bit 4) to confirm the rotation occurred.

Resynchronizing LMFC Signals

If desired, the sync procedure can be repeated to realign the

LMFC clock to the reference signal by repeating Step 2 to Step 6,

described in the Sync Procedure section. When the one‑shot sync

is triggered (writing Register 0x03A = 0x02), the SYNCOUTx±

signals deassert to drop the JESD204B links and reassert the links

after the rotation completes.

Deterministic Latency

JESD204B systems contain various clock domains distributed

throughout. Data traversing from one clock domain to a different

clock domain can lead to ambiguous delays in the JESD204B link.

These ambiguities lead to nonrepeatable latencies across the link

from power cycle to power cycle with each new link establishment.

Section 6 of the JESD204B specification addresses the issue of

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