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H838024 Datasheet(PDF) 241 Page - Renesas Technology Corp |
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H838024 Datasheet(HTML) 241 Page - Renesas Technology Corp |
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241 / 697 page ![]() Section 8 I/O Ports Rev. 7.00 Mar 10, 2005 page 199 of 652 REJ09B0042-0700 This section only deals with the bits related to timer G and the watchdog timer. For the functions of the bits, see the descriptions of port 3 (POF1) and port 4 (IRQ0). Bit 2—Watchdog Timer Source Clock (WDCKS) This bit selects the watchdog timer source clock. Note that stabilization times for the H8/38024, H8/38024S, and H8/38024R Group and for the H8/38124 Group are different. • H8/38024, H8/38024S, H8/38024R Group Bit 2 WDCKS Description 0 Selects φ/8192 (initial value) 1 Selects φ W/32 • H8/38124 Group Bit 2 WDCKS Description 0 Selects clock based on timer mode register W (TMW) setting* (initial value) 1 Selects φ W/32 Note: * See section 9.6, Watchdog Timer, for details. Bit 1—TMIG Noise Canceller Select (NCS) This bit selects controls the noise cancellation circuit of the input capture input signal (TMIG). Bit 1 NCS Description 0 No noise cancellation circuit (initial value) 1 Noise cancellation circuit |
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