AM69 datasheet(276/312 Pages) TI

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7 Detailed Description

7.1 Overview

The AM69, AM69A processor family is based on the evolutionary Jacinto 7 architecture, targeted at ADAS and

Autonomous Vehicle (AV) applications and built on extensive market knowledge accumulated over a decade of

TI’s leadership in the ADAS processor market. The AM69, AM69A provides high performance compute for both

traditional and deep learning algorithms at industry leading power/performance ratios with a high level of system

integration to enable scalability and lower costs for advanced automotive platforms supporting multiple sensor

modalities in centralized ECUs or stand-alone sensors. Key cores include next generation DSP with scalar and

vector cores, dedicated deep learning and traditional algorithm accelerators, latest Arm and GPU processors

for general compute, an integrated next generation imaging subsystem (ISP), video codec, Ethernet hub and

isolated MCU island. All protected by automotive grade safety and security hardware accelerators.

Note

For more information on features, subsystems, and architecture of superset device System on Chip

(SoC), see the device TRM.

7.2 Functional Block Diagram

Figure 7-1 is functional block diagram for the device.

Note

To understand what device features are currently supported by TI Software Development Kits (SDKs),

see the AM69 Software Build Sheet (PROCESSOR-SDK-AM69) and AM69A Software Build Sheet

(PROCESSOR-SDK-AM69A).

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

www.ti.com

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AM69 Datasheet(PDF) 276 Page - Texas Instruments