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6.10.6.2.1.2 JTAG Switching Characteristics

See Figure 6-112

NO.

PARAMETER

MIN

MAX

UNIT

td(TCKL-TDOI)

Delay time minimum, TCK low to TDO invalid

td(TCKL-TDOV)

Delay time maximum, TCK low to TDO valid

1. The JTAG signals are split across two IO power domains on the device. Timings parameters defined in

this table only apply when the two IO power domains are operating at the same voltage. Values for these

timing parameters are not defined when operating the two IO power domains at different voltages since

propagation delay through the device IO buffers differ when some are operating at 1.8V while others are

operating at 3.3V. This effectively reduces timing margin beyond the values defined in this table. The JTAG

interface is still expected to function when the two IO power domains are operated at different voltages,

assuming the system designer has implemented appropriate level shifters and the operating frequency is

reduced to accommodate additional delay inserted by the level-shifters and IO buffers operating at different

voltages.

TDO

TCK

TDI / TMS

Figure 6-112. JTAG Timing Requirements and Switching Characteristics

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AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

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AM69 Datasheet(PDF) 275 Page - Texas Instruments