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6.10.6.2 JTAG

For more details about features and additional description information on the device IEEE 1149.1 Standard–

Test–Access Port, see the corresponding sections within Signal Descriptions and Detailed Description.

Note

The JTAG signals are split across two IO power domains on the device. Timings parameters defined

in this section only apply when the two IO power domains are operating at the same voltage and level-

shifters are not inserted into the signal path. Values for the following timing parameters are not defined

when operating the two IO power domains at different voltages since propagation delay through the

device IO buffers differ when some are operating at 1.8 V while others are operating at 3.3 V. This

effectively reduces timing margin beyond the values defined in this section. The JTAG interface is still

expected to function when the two IO power domains are operated at different voltages, assuming the

system designer has implemented appropriate level-shifters and the operating frequency is reduced

to accommodate additional delay inserted by the level-shifters and IO buffers operating at different

voltages.

Table 6-94. JTAG Timing Conditions

PARAMETER

MIN

MAX

UNIT

Input Conditions

SRI

Input slew rate

0.50

2.00

V/ns

Output Conditions

Output load capacitance

PCB CONNECTIVITY REQUIREMENTS

td(Trace Delay)

Propagation delay of each trace

83.5

1000(1)

td(Trace Mismatch Delay)

Propagation delay mismatch across all traces

100

(1)

Maximum propagation delay associated with the JTAG signal traces has a significant impact on maximum TCK operating frequency. It

may be possible to increase the trace delay beyond this value, but the operating frequency of TCK must be reduced to account for the

additional trace delay.

6.10.6.2.1 JTAG Electrical Data and Timing

Section 6.10.6.2.1.1, Section 6.10.6.2.1.2, and Figure 6-112 assume testing over the recommended operating

conditions and electrical characteristic conditions.

6.10.6.2.1.1 JTAG Timing Requirements

See Figure 6-112

NO.

MIN

MAX UNIT

tc(TCK)

Cycle time minimum, TCK

46.5(1)

tw(TCKH)

Pulse width minimum, TCK high

18.6(2)

tw(TCKL)

Pulse width minimum, TCK low

18.6(2)

tsu(TDI-TCK)

Input setup time minimum, TDI valid to TCK high

4.5

tsu(TMS-TCK)

Input setup time minimum, TMS valid to TCK high

4.5

th(TCK-TDI)

Input hold time minimum, TDI valid from TCK high

th(TCK-TMS)

Input hold time minimum, TMS valid from TCK high

(1)

The maximum TCK operating frequency assumes the following timing requirements and switching characteristics for the attached

debugger. The operating frequency of TCK must be reduced to provide appropriate timing margin if the debugger exceeds any of these

assumptions.

•

Minimum TDO setup time of 4.6 ns relative to the rising edge of TCK

•

TDI and TMS output delay in the range of –16.5 ns to 14.0 ns relative to the falling edge of TCK

(2)

P = TCK cycle time in ns

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

www.ti.com

274

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