AM69 datasheet(272/312 Pages) TI

272 / 312 page

Table 6-91. UART Timing Conditions (continued)

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

SRI

Input slew rate

0.5

V/ns

OUTPUT CONDITIONS

Output load capacitance

30(1)

(1)

This value represents an absolute maximum load capacitance. As the UART baud rate increases, it may be necessary to reduce the

load capacitance to a value less than this maximum limit to provide enough timing margin for the attached device. The output rise/fall

times increase as capacitive load increases, which decreases the time data is valid for the receiver of the attached devices. Therefore,

it is important to understand the minimum data valid time required by the attached device at the operating baud rate. Then use the

device IBIS models to verify the actual load capacitance on the UART signals does not increase the rise/fall times beyond the point

where the minimum data valid time of the attached device is violated.

Section 6.10.5.23.1, Section 6.10.5.23.2, and Figure 6-110 present timing requirements and switching

characteristics for UART interface.

6.10.5.23.1 Timing Requirements for UART

NO.

PARAMETER

DESCRIPTION

MODE

MIN

MAX

UNIT

tw(rxd)

Pulse width, receive data bit, high or low

0.95U(1)

(2)

1.05U(1)

(2)

tw(rxdS)

Pulse width, receive start bit, low

0.95U(1)

(2)

(1)

U = UART baud time = 1/Programmed baud rate

(2)

This value defines the data valid time, where the input voltage is required to be above VIH or below VIL.

6.10.5.23.2 UART Switching Characteristics

NO.

PARAMETER

DESCRIPTION

MIN

MAX

UNIT

f(baud)

Maximum programmable baud rate

Mbps

tw(TX)

Pulse width, transmit data bit, high or low

U - 2(1)

U + 2(1)

tw(RTS)

Pulse width, transmit start bit, high or low

U - 2(1)

(1)

U = UART baud time = 1/Programmed baud rate

UARTi_TXD

Start

Bit

Data Bits

UARTi_RXD

Data Bits

Bit

Start

UART_TIMING_01_RCVRVIHVIL

Figure 6-110. UART Timing

For more information, see Universal Asynchronous Receiver/Transmitter (UART) section in Peripherals chapter

in the device TRM.

6.10.5.24 USB

The USB 2.0 subsystem is compliant with the Universal Serial Bus (USB) Specification, revision 2.0. Refer to the

specification for timing details.

AM69A, AM69

SPRSP92C – FEBRUARY 2023 – REVISED JUNE 2024

www.ti.com

272

Submit Document Feedback

Product Folder Links: AM69A AM69

AM69 Datasheet(PDF) 272 Page - Texas Instruments

AM69 Datasheet(HTML) 272 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL