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PM8621 Datasheet(PDF) 60 Page - PMC-Sierra, Inc |
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PM8621 Datasheet(HTML) 60 Page - PMC-Sierra, Inc |
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60 / 184 page  NSE-8G™ Standard Product Data Sheet Preliminary Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 59 Document ID: PMC-2010850, Issue 1 Register 001H: NSE-8G Individual Channel Reset Bit Type Function Default Bit 11:0 R/W RESET[11:0]* 1 This register allows power saving by holding individual channels in reset. RESET[n] The RESET[n] bit allows the channel circuitry in the NSE-8G to be reset under software control. If the RESET[n] bit is a logic one, the NSE-8G channel circuitry for a particular channel is held in reset. RESET[n] does not affect the reset of the CSU. This bit is not self- clearing. Therefore, a logic zero must be written to bring the channel out of reset. Holding the channel in a reset state places it into a low power, analog stand-by mode. A hardware reset or software DRESET bit 000h sets the RESET[n] bit. |
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