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PM8621 Datasheet(PDF) 84 Page - PMC-Sierra, Inc |
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PM8621 Datasheet(HTML) 84 Page - PMC-Sierra, Inc |
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84 / 184 page  NSE-8G™ Standard Product Data Sheet Preliminary Proprietary and Confidential to PMC-Sierra, Inc., and for its Customers’ Internal Use 83 Document ID: PMC-2010850, Issue 1 Register 021H, 025H: CSTR #1 – 2* Interrupt Enable and CSU Lock Status Bit Type Function Default Bit 31-2 R Unused X Bit 1 R LOCKV X Bit 0 R/W LOCKE 0 This register configures the operation of CSTR block #1. LOCKE The CSU lock interrupt enable bit (LOCKE) controls the contribution of CSU lock state interrupts by the CSTR to the device interrupt INTB. When LOCKE is high, INTB is asserted low when the CSU lock state changes. Interrupts due to CSU lock state are masked when LOCKE is set low. LOCKV The CSU lock status bit (LOCKV) indicates whether the clock synthesis unit has successfully locked with the system clock. LOCKV is set low when the CSU has not successfully locked with the reference clock. LOCKV is set high if when the CSU has locked with the reference clock. |
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